DRAM Interface MDQ Receive Enable Phase (MREP) Training - 1.0 English

Versal Adaptive SoC Programmable Network on Chip and Integrated Memory Controller 1.0 LogiCORE IP Product Guide (PG313)

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1.0 English

This training aligns the Read MDQS phase with the data buffer clock. In this training mode, the host sends a sequence of read commands, the DRAM sends out the MDQS, the data buffer samples the strobe with the clock, and feeds back the result on DQ. Calibration continues to perform this training to find the 0 to 1 transition on Read MDQS sampled with the data buffer clock.