HBM Topology - 1.0 English

Versal Adaptive SoC Programmable Network on Chip and Integrated Memory Controller 1.0 LogiCORE IP Product Guide (PG313)

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The HBM solutions are available in either 8 GB or 16 GB per-stack options, with most configurations containing two stacks per device. This means there is a total of 8 GB of available memory on a single-stack device, and 16 GB or 32 GB of available memory on dual-stack devices.

The total data-bit width of an HBM stack is 1024 bits divided across eight channels of 128 bits each. Each channel is serviced by a single HBM controller which accesses the HBM in pseudo channel mode, meaning two semi-independent 64-bit data channels with a shared command/address/control (CAC) bus. An 8 GB per-stack device has 8 Gb per channel, and each channel has two 4 Gb or 512 MB pseudo channels. A 16 GB per-stack device has access to 16 Gb or 2 GB per channel, and each channel has two 8 Gb or 1 GB pseudo channels.

The HBM always operates with a burst length of 4 in pseudo channel mode. The HBM protocol closely matches that of DDR4 memory, so many of the same performance and protocol concepts apply. The clock rate of the HBM is set in the IP configuration options in the AMD Vivado™ IDE. HBM is a double data rate (DDR) memory, so the data bus toggles at twice the interface clock rate.