DRAM Power Down - 1.0 English

Versal Adaptive SoC Programmable Network on Chip and Integrated Memory Controller 1.0 LogiCORE IP Product Guide (PG313)

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1.0 English

The Versal Memory Controller supports activity-based DRAM Power Down. When the Memory Controller has been idle for a programmable amount of clock cycles, it will drive the DRAM CKE low to enter power down mode. The DRAM will be periodically taken out of power down mode as required for refresh operations or for ECC scrubbing. The DRAM will be taken out of power down mode automatically when memory transactions are received. This will have a delay of about 50 memory clock cycles.