Address Decoding and the System Address Map - 1.0 English

Versal Adaptive SoC Programmable Network on Chip and Integrated Memory Controller 1.0 LogiCORE IP Product Guide (PG313)

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The AMD Versal™ adaptive SoC programmable NoC system address map defines the default address locations of slaves in the Versal device. The address map is built into the integrated interconnect of the NoC. The NoC provides some capabilities to perform address re-mapping which allow the address map to be customized to the target application.

The following table shows the top level of the system address map from the NoC perspective.

Table 1. System Address Map
Name Start Address End Address Description
DDR_LOW0 0x0000_0000_0000 0x0000_7FFF_FFFF DDR Channel 0 subregion 0
LPD_AFI_FS 0x0000_8000_0000 0x0000_9FFF_FFFF Access to the PL via the low power domain AFI port
reserved 0x0000_A000_0000 0x0000_A3FF_FFFF Not decoded
FPD_AFI_0 0x0000_A400_0000 0x0000_AFFF_FFFF Access to the PL via the full power domain AFI port
FPD_AFI_1 0x0000_B000_0000 0x0000_BFFF_FFFF Access to the PL via the full power domain AFI port
QSPI 0x0000_C000_0000 0x0000_DFFF_FFFF Access to the QSPI/OSPI interface
PCIe_0 0x0000_E000_0000 0x0000_EFFF_FFFF Access to PCIe region 0
PMC 0x0000_F000_0000 0x0000_F7FF_FFFF Access to the PMC slave devices
STM_CORESIGHT 0x0000_F800_0000 0x0000_F90F_FFFF Access to the CoreSight STM and the GIC programming interface
reserved 0x0000_F910_0000 0x0000_FBFF_FFFF Not decoded
CPM 0x0000_FC00_0000 0x0000_FCFF_FFFF Access to the CPM block
FPD_SLAVES 0x0000_FD00_0000 0x0000_FDFF_FFFF Access to slave devices in the full power domain
LPD_SLAVES 0x0000_FE00_0000 0x0000_FFFF_FFFF Access to slave devices in the low power domain
PMC_ALIAS_0 0x0001_0000_0000 0x0001_07FF_FFFF Access to the PMC on the master die via NoC from other die on SSIT devices
PMC_ALIAS_1 0x0001_0800_0000 0x0001_0FFF_FFFF Access to the PMC on the die 1 via NoC and from other die on SSIT devices
PMC_ALIAS_2 0x0001_1000_0000 0x0001_17FF_FFFF Access to the PMC on the die 2 via NoC and from other die on SSIT devices
PMC_ALIAS_3 0x0001_1800_0000 0x0001_1FFF_FFFF Access to the PMC on the die 3 via NoC and from other die on SSIT devices
reserved 0x0001_2000_0000 0x0003_FFFF_FFFF Not decoded
PS_TO_PL_0 0x0004_0000_0000 0x0005_FFFF_FFFF Access from the PS to the PL via the AFI interface
PCIe_1 0x0006_0000_0000 0x0007_FFFF_FFFF Access to PCIe region 1
DDR_LOW1 0x0008_0000_0000 0x000F_FFFF_FFFF DDR Channel 0 subregion 1
reserved 0x0010_0000_0000 x003F_FFFF_FFFF Not decoded
HBM_memory 0x0040_0000_0000 0x0047_FFFF_FFFF HBM Address Space
reserved 0x0048_0000_0000 0x007F_FFFF_FFFF Not decoded
PCIe_2 0x0080_0000_0000 0x00BF_FFFF_FFFF Access to PCIe region 2
DDR_LOW2 0x00C0_0000_0000 0x00FF_FFFF_FFFF DDR Channel 0 subregion 2
DDR_LOW3 0x0100_0000_0000 0x01B7_7FFF_FFFF DDR Channel 0 subregion 3
reserved 0x01B7_8000_0000 0x01FF_FFFF_FFFF Not decoded
AIE 0x0200_0000_0000 0x0200_3FFF_FFFF Access to the AI Engine array
Reserved 0x0200_8000_0000 0x0200_FFFF_FFFF Not decoded
PL_LO 0x0201_0000_0000 0x03FF_FFFF_FFFF Access to slave devices in the PL, low address region
reserved 0x0400_0000_0000 0x04FF_FFFF_FFFF Not decoded
DDR_CH1 0x0500_0000_0000 0x057F_FFFF_FFFF Low half of DDR Channel 1
DDR_CH1_1 0x0580_0000_0000 0x05FF_FFFF_FFFF High half of DDR Channel 1
DDR_CH2 0x0600_0000_0000 0x067F_FFFF_FFFF Low half of DDR Channel 2
DDR_CH2_1 0x0680_0000_0000 0x06FF_FFFF_FFFF High half of DDR Channel 2
DDR_CH3 0x0700_0000_0000 0x077F_FFFF_FFFF Low half of DDR Channel 3
DDR_CH3_1 0x0780_0000_0000 0x07FF_FFFF_FFFF High half of DDR Channel 3
PL_HI 0x0800_0000_0000 0x0FFF_FFFF_FFFF Slave devices in the PL, high address region
reserved 0x1000_0000_0000 0xFFFF_FFFF_FFFF Not decoded

Address Regions

Address region DDR_CH0 comprises multiple subregions: DDR_LOW0, DDR_LOW1, DDR_LOW2, and DDR_LOW3, totaling 1 TB of space. The low 2 GB of that space, DDR_LOW0, is addressable by 32-bit address masters. Address regions DDR_CH1, DDR_CH2, and DDR_CH3 each may be divided into two subregions that can map to independent memory controllers.
The various CIPS slave regions (LPD_AFI_FS, FPD_AFI_0, FPD_AFI_1, QSPI, PCIe_0, PMC, STM_CORESIGHT, CPM, FPD_SLAVES, and LPD_SLAVES) have fixed address regions within the low 4 GB of the address space to allow for access by 32-bit masters.
The PMC_ALIAS regions provide access to the address space of the PMC block in one SLR from masters in other SLRs. For example, access to the PMC in SLR1 from SLR0 would be through the PMC_ALIAS_1 address region.
The PS_to_PL address region provides direct access from masters in the PS to slaves in the PL through the AFI interface. This region is not accessible from the NoC.
The AIE, PL_LO, and PL_HI regions do not have dedicated address decoders. Transactions to these regions must use the fixed destination ID, a master defined destination ID, or an address remap register.

Address assignment is handled through the Address Editor in AMD Vivado™ . The Address Editor chooses addresses within defined apertures. By default, the Address Editor assigns a unique 1 GB aperture within PL_LO to each PL NSU within a block design. Address assignments can be edited within the Address Editor, and apertures can be edited in the NSU Block Interface Properties window in Vivado. The Address Editor will automatically adjust apertures when an address assignment is edited, with a few exceptions related to NSUs connected to an NMU connected to CCI.

Access from CCI to PL_LO and PL_HI requires special attention. Access to PL_LO is non-interleaved. Refer to the Address Mapping section of the Versal Adaptive SoC Technical Reference Manual (AM011) for details about which CCI ports to use. Access to PL_HI is interleaved. To access PL_HI from CCI, first unassign addresses from all four CCI NMUs to the desired NSU, then manually edit the NSU aperture to point to the PL_HI address range, and finally reassign address in the Address Editor. For more details refer to the Vivado Design Suite User Guide: Designing IP Subsystems using IP Integrator (UG994).

Any access to the PL region should follow address remapping rules (refer to Address Remap Tab). If a transaction is being routed using the AXI address and the incoming address does not hit in any address matcher or fall in the AIE, PL_LO, or PL_HI spaces, an AXI DECERR is generated and an interrupt status bit is set to indicate an address map error. Transactions that fall in the AIE, PL_LO, or PL_HI spaces but do not hit in a remap register and hence, do not receive a valid destination ID can still be injected into the NoC routing fabric. In this case, an NSU can be configured as an error slave to receive such invalid transactions. The error slave is configured to return a DECERR instead of a SLVERR.

NPI Addressing

The NoC and DDRMC are configured via the NPI interface in each PMC. For register descriptions, see Versal Adaptive SoC NoC and Integrated Memory Controller NPI Register Reference (AM019).

For lists of addresses and NoC site locations, see AR 000035076.