- DDR4 and LPDDR4/4X protocols.
- Component, SODIMM, UDIMM, RDIMM, LRDIMM topology support.
- Up to x64 data width or x72 for ECC interfaces.
- Up to x32 data width for dual channel configurations.
- Supports up to 4H DDR4 3DS Logical Ranks.
- Supports Multi-Rank and Dual Slot topologies.
- Quality of Service (QoS) classes:
- Read: Isochronous, Low Latency, Best Effort.
- Write: Isochronous, Best Effort.
- Out-of-order execution of commands for enhanced SDRAM efficiency.
- ECC support: Single Error Correct, Dual Error Detect:
- On-the-fly scrubbing.
- Background scrubbing.
- Correctable and uncorrectable error logging.
- Error injection for writes.
- Address Parity.
- Data Mask and Dynamic Bus Inversion (DBI).
- Fixed Burst Length 8 for DDR4.
- Fixed Burst Length 16 for LPDDR4.
- 1T or 2T timing for Address/Command bus.
- Refresh support for 1x, 2x, and 4x rates.
- No support for on-the-fly refresh rate control as a function of temperature.
- 2x and 4x fine granularity refresh modes for DDR4.
- Per-Bank refresh for LPDDR4/4X.
- Read-After-Write and Write-After-Write hazard checking.
- AXI ID ordering.