Clocking - 1.0 English

Versal Adaptive SoC Programmable Network on Chip and Integrated Memory Controller 1.0 LogiCORE IP Product Guide (PG313)

Document ID
PG313
Release Date
2024-05-30
Version
1.0 English

The reference clock for the PLL can be provided from an internal clock sourced by CIPS (HSM0 of the HBM SLR), or from dedicated clock pins in the same IO bank as the HBM (800 and 801). Based on the input clock frequency provided and the desired operation rate of the HBM, the dedicated PLL will be automatically configured to match the requirements.

There is a Differential Clock Capable IO (CCIO) pin which is used to provide the reference clock of 100 MHz to 500 MHz from external source to the PLL. There are two IO standards supported: LVCMOS and LVDS. The dedicated clock pair are C4CCIO_PAD0 and _PAD1. C4CCIO_PAD0 is the P-side and _PAD1 is the N-side of the LVDS differential pair. When used as single ended, the clock should be connected to C4CCIO_PAD0 and configured as LVCMOS12.

Internal clock source (HSM0) has a range of 100-200 MHz and the external clock has a range of 100-500 MHz. Internal clocking is preferred for ease of use, as the HBM clock is sourced from the CIPS, eliminating the need for an externally routed reference clock. When this option is selected, a single clock from the CIPS (HSM0 of the HBM SLR) is used as the reference clock for both HBM stacks. External clocking is supported for flexibility, allowing two independent clocks to be provided by the user, one for each stack. There are no frequency or phase dependencies between the two clocks.

Refer to the Versal HBM Series Data Sheet: DC and AC Switching Characteristics (DS960) for information on supported data rates.