Periodic Writes - 1.0 English

Versal Adaptive SoC Programmable Network on Chip and Integrated Memory Controller 1.0 LogiCORE IP Product Guide (PG313)

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1.0 English

LPDDR4 systems align write DQS with DQ during calibration, to account for mismatched receiver delay paths within the DRAM. This alignment must also be periodically adjusted to account for drift over time, and this requires periodic writes to memory. Hence, for LPDDR4 systems, the controller will issue both periodic reads and periodic writes with an interval of 20 μs.

Memory access patterns with long continuous reads will have a small efficiency impact as a write operation will create a read-write turnaround delay. If the memory access contains a mix of read and write commands, provided two writes are within 20 μs of each other, the controller will not need to insert any periodic writes. An important point to note is that the simulation does not account for the periodic writes or reads, regardless of whether the design is LP4DDR4 or DDR4. Hence, there will be a minor bandwidth mismatch between simulation and hardware.