Memory Configuration Support - 1.1 English

Versal Adaptive SoC Programmable Network on Chip and Integrated Memory Controller 1.1 LogiCORE IP Product Guide (PG313)
Document ID
PG313
Release Date
2024-08-09
Version
1.1 English
Table 1. DDR4 Component Interface
DDR Channels Data Bus Width Data Bus Width with ECC DRAM Component Max. Number of Ranks
1 64 72 DDR4: x8, x16 DDR4 3DS: x8 1 SDP, 2 DDP
1 32 40 DDR4: x4, x8, x16 DDR4 3DS: x4, x8 1 SDP, 2 DDP
1 16 24 DDR4: x4, x8, x16 DDR4 3DS: x4, x8 1 SDP, 2 DDP
2 2 32 N/A DDR4: x8, x16 DDR4 3DS: x8 1 SDP, 2 DDP
2 2 16 24 DDR4: x8, x16 DDR4 3DS: x8 1 SDP, 2 DDP
  1. For any component interface, all memory components must be identical.
  2. Some devices use a shared read reorder buffer for dual channel configuration, and read efficiency will be affected. Refer to Reordering for more information.
  3. Multi-rank for component interfaces is only supported for dual-die packages. Sharing the DQ bus with multiple components as separate physical ranks on the PCB is not supported.
Table 2. DDR4 DIMM Interface
Data Bus Width Data Bus Width with ECC DIMM Type Max. Number of Physical Ranks per DIMM Max Number of Slots
64 72 RDIMM with DDR4 or DDR4 3DS 2 2
64 72 UDIMM/SODIMM with DDR4 2 1
64 72 LRDIMM with DDR4 or DDR4 3DS 4 1
64 72 LRDIMM with DDR4 or DDR4 3DS 2 2
  1. For any DIMM interface with multiple slots, all DIMMs must be identical.
Table 3. LPDDR4/4X Component Interface
LPDDR4/4X Channels Data Bus Width Data Bus Width with ECC DRAM Component 1 Max. Number of Ranks 3
1 32 48 LPDDR4/4X : x32, x16 2
1 16 32 LPDDR4/4X : x32, x16 2
2 2 32 N/A LPDDR4/4X : x32, x16 2
2 2 16 32 LPDDR4/4X : x32, x16 2
  1. For any component interface, all memory components must be identical on a x16 channel basis. A mix of dual-channel (x32) devices and single-channel (x16) devices can be used, but the memory density per x16 channel must match between all devices. Byte-mode devices are not supported.
  2. Some devices use a shared read reorder buffer for dual channel configuration, and read efficiency will be affected. Refer to Reordering for more information.
  3. Dual-rank for component interfaces is only supported for dual-rank packages. Sharing the DQ bus with two discrete components as separate physical ranks on the PCB is not supported. Pin Efficient interfaces only support single rank.