LRDIMM MRD Cycle Training - 1.0 English

Versal Adaptive SoC Programmable Network on Chip and Integrated Memory Controller 1.0 LogiCORE IP Product Guide (PG313)

Document ID
Release Date
1.0 English

This training finds the correct cycle to maintain the set Read Latency value at the data buffer. In this training mode, the controller pre-programs the data buffer MPR registers with the expected pattern and issues read commands. The data buffer compares the read data with the expected data and feeds back the result on the DQ bus. Calibration selects the correct cycle based on the result of the comparison.

There are no debug registers associated with this calibration stage.