DB-to-DRAM Write Delay (MWD) Center Training - 1.0 English

Versal Adaptive SoC Programmable Network on Chip and Integrated Memory Controller 1.0 LogiCORE IP Product Guide (PG313)

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1.0 English

This training center aligns Write MDQS in the Write MDQ window at the DRAM. In this training mode, the host pre-programs the data buffer MPR registers with the expected pattern, issues write commands to load the data into memory, and issues reads to the memory. The data buffer compares the read data with the expected data and feeds back the result on the DQ bus. Calibration finds the left and right edges of the MDQ valid window and centers MDQS in it.