The integrated DDRMC can also be configured as two independent DDR interfaces of 16 or 32 data bits each. This section describes the Non-Flipped pin efficient 2x32 LPDDR4/4X interface.
Figure 1. Connections for a Pin Efficient 2x32 LPDDR4/4x Interface
Nibble utilization for pin efficient 2x32 interface using two x32 components in the non-flipped configuration is shown in the following figure. DQ indicates data nibbles, AC indicates Address/Command/Control nibbles, sys_clk indicates a nibble comprising the System Clock pair, RESET_n, and ALERT_n signals. Refer to Clocking for System Clock details.
Important: The
nibble utilization figure is based on the fixed pinout output by Vivado for this configuration.
Note:
For LPDDR4/LPDDR4x pin efficient configurations, different IO standards for
reset_n other than those recommended by Vivado are allowed, and the warning reported by Vivado can be ignored.
Figure 2. Nibble Utilization for Pin Efficient 2x32 Component Interface
(Non-Flipped)
