You can also configure the integrated DDRMC as two independent DDR interfaces of 16 or 32 data bits each. This section describes the Non-Flipped pin efficient 2x32 LPDDR4/4X interface.
Figure 1. Connections for a Pin Efficient 2x32 LPDDR4/4x Interface
The following figure shows the nibble utilization for a pin efficient 2x32
interface using two x32 components in the non-flipped configuration. DQ indicates
data nibbles. AC indicates Address/Command/Control nibbles. sys_clk
indicates a nibble comprising the System Clock pair, RESET_n, and ALERT_n signals.
Refer to Clocking for System Clock
details.
Important: The
nibble utilization figure is based on the fixed pinout output by Vivado for this configuration.
Note:
For LPDDR4/LPDDR4x pin efficient configurations, different IO standards for
reset_n other than Vivado recommends are allowed. You can ignore
the warning Vivado reports.
Figure 2. Nibble Utilization for Pin Efficient 2x32 Component Interface
(Non-Flipped)
