Read DBI Calibration - 1.0 English

Versal Adaptive SoC Programmable Network on Chip and Integrated Memory Controller 1.0 LogiCORE IP Product Guide (PG313)

Document ID
PG313
Release Date
2024-05-30
Version
1.0 English

Calibration Overview

If the read DBI option is selected for DDR4, the DBI pin needs to be calibrated along with the DQ bits being captured.

The regular deskew algorithm performs a per-bit deskew on every DQ bit in a nibble against the PDQS/NDQS, pushing early DQ bits to line up with late bits. Because the DBI pin is an input to one of the nibbles, it could affect the PQTR/NQTR settings or even the other DQ pins if the DQ pins need to be pushed to align with the DBI pin. A similar mechanism as the DQ per-bit deskew is ran but the DBI pin is deskewed instead in relation to the PDQS/NDQS.

DBI deskew calibration algorithm is started after the completion of read and write per bit DQ deskew calibration step. Pattern 10101010 is written in the memory and read back with DBI mode enabled. Because DBI mode is enabled, instead of driving 10101010 on data lines DRAM drives static 1 and 10101010 on the DBI line.

  1. Turn on DBI on the read path (MRS setting in the DRAM and a fabric switch that inverts the read data when value read from the DBI pin is asserted).
  2. If the nibble does not contain the DBI pin, skip the nibble and go to the next nibble.
  3. Start from the previous PQTR/NQTR settings found during DQS to DQ centering.
  4. Issue back-to-back reads to address where pattern 10101010 is written. This is repeated until per-bit DBI deskew is complete as shown in the figure below.
    Figure 1. DBI Deskew Read Pattern
  5. Confirm PDQS and NDQS are sampling valid region of DBI.
    • If they are not sampling the valid region, then DBI is delayed until they start sampling the valid region with the minimum valid window confirmation.
    • If they are already sampling the valid region, then only the minimum valid window confirmation is required.
  6. After completion of step 5, DBI continues to be delayed until the PDQS and the NDQS start sampling the noise region of the DBI.
  7. The delay taps used for DBI in step 6 + the minimum valid window taps is called left margin of the DBI.
  8. Revert the DBI delay taps equal to the left margin.
  9. Start incrementing the delay taps of the DQ lines and PDQS/NDQS until PDQS and NDQS start sampling the noise region of the DBI.
  10. The used delay taps in the step 9 is called right margin of the DBI.
  11. Revert all the delay taps of the step 9.
  12. Compare left margin versus the right margin.
    • If the left margin is bigger than the right margin, then add delay equal to (left margin – right margin) / 2 to the DBI delay lines.
    • If the right margin is bigger than the left margin, then add delay equal to (right margin – left margin) / 2 to the DQ IDELAY, PQTR, and NQTR.
  13. Loop through all nibbles in the interface for the rank.
  14. Turn off DBI on the read path (MRS setting in the DRAM and fabric switch).
There are no debug registers associated with this calibration stage.