Address Parity - 1.0 English

Versal Adaptive SoC Programmable Network on Chip and Integrated Memory Controller 1.0 LogiCORE IP Product Guide (PG313)

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1.0 English

The Versal Memory Controller supports Address and Command Parity for DDR4. If a parity error is detected by the DRAM, ALERT_n will be driven low and detected by the memory controller and the controller will halt all traffic and attempt a re-try of the failed command. This requires significant effort by the controller and physical interface (PHY) to recover and re-try. The PHY buffers need to be flushed, which may have a latency impact of several microseconds. As a result, isochronous latency is not guaranteed, and bandwith requirements may not be met in this scenario. If an ALERT_n is detected during the retry attempt, the memory controller will issue a fatal interrupt. The DDRMC cannot recover from an ALERT_n event during retry. A system reboot is needed and memory contents is lost.