The Versal Memory Controller supports Address
and Command Parity for DDR4. If a parity error is detected by the DRAM, ALERT_n is driven low and detected by the memory controller
and the controller halts all traffic and attempt a re-try of the failed command. This
requires significant effort by the controller and physical interface (PHY) to recover
and re-try. The PHY buffers need to be flushed, which can have a latency impact of
several microseconds. As a result, isochronous latency is not guaranteed, and bandwith
requirements might not be met in this scenario. If an ALERT_n is detected during the retry attempt, the memory controller issues
a fatal interrupt. The DDRMC cannot recover from an ALERT_n event during retry. A system reboot is needed and memory contents
is lost.