QoS Tab - 1.1 English - PG313

Versal Adaptive SoC Programmable Network on Chip and Integrated Memory Controller 1.1 LogiCORE IP Product Guide (PG313)

Document ID
PG313
Release Date
2024-11-13
Version
1.1 English

The Quality of Service (QoS) tab of the Customize IP dialog box is shown in the following figure. This tab allows the configuration of the quality of service properties of every stream path defined in the axis_noc instance.

Figure 1. QoS Tab

The left column of the QoS tab shows a tree structure of the connectivity defined in the Connectivity tab. The top of each tree (left aligned port names) are the NoC ingress ports; in the figure S00_AXIS. Shown under each ingress port are the associated rows for each connected egress port.

The second column defines the write traffic class. The possible values are ISOCHRONOUS and BEST_EFFORT (default). The traffic class applies to all connections originating from the given ingress port.

The third column indicates whether this NoC instance owns the QoS setting for a given path. A NoC path may go through multiple NoC instances using INI. QoS settings are taken from the NoC instance that owns the QoS and path. QoS is ignored when a NoC instance does not own the path. Ownership is at the transition from an NMU or strategy=Driver to an NSU or strategy=Load. A value of 'pending' means the ownership will be calculated during validate, or by clicking the Run NoC DRCs button above. For a value of 'error', validate or click the Run NoC DRCs button above to see error details in the Tcl Console and messages window.

The fourth column defines the Write Bandwidth expressed in MB/s or Gb/s. Allowed values range from 0 (no Write traffic is accepted) to the maximum data bandwidth of the NoC physical channel.

The QoS tab Advanced check box enables additional columns that are described in QoS Tab.

Note: After validation the NoC QOS tab will populate with read and write latency estimates. The Read Latency Estimate and Write Latency Estimate represent only the round-trip structural latency through a portion of the NoC in the NoC clock domain. These numbers do not include latency in the DRAM, memory controller, PCB routing, etc. The actual total latency will be greater than these numbers. These latencies are reported in NoC clock cycles. They are intended for relative comparison between different NoC implementations, not as a representation of the actual total latency.