NMU Selections - 1.0 English

Versal Adaptive SoC Programmable Network on Chip and Integrated Memory Controller 1.0 LogiCORE IP Product Guide (PG313)

Document ID
PG313
Release Date
2024-05-30
Version
1.0 English

This section explains the system design considerations to get the most performance out of Versal HBM solutions. As discussed previously, the HBM_NMU connects the PL fabric array to the HBM controllers, helping utilize the maximum bandwidth available for the HBM subsystem. Access from any other NMU (NMU512) is also available, but bandwidth may be limited by the NoC capacity.