Vivado Hardware Manager – Memory Debug - 1.0 English

Versal Adaptive SoC Programmable Network on Chip and Integrated Memory Controller 1.0 LogiCORE IP Product Guide (PG313)

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1.0 English

After programming, the AMD Vivado™ Hardware Manager displays all debug IP which includes integrated memory interfaces. This provides information such as memory IP configuration, status of calibration, calibration errors, and read/write window margin data. This information can be viewed through the GUI or extracted to text files via Tcl.

Note: These properties are read back only once, either upon completion of programming, or initial connection to an already programmed device. They are not regularly updated, so if any actions have been done to change the configuration after initial programming, you should refresh the device to re-download the latest properties. To do this, right-click on the device and select Refresh Device.