DDR Basic Tab - 1.0 English

Versal Adaptive SoC Programmable Network on Chip and Integrated Memory Controller 1.0 LogiCORE IP Product Guide (PG313)

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1.0 English
The DDR Basic tab is shown in the following figure for reference.
Figure 1. DDR Basic Tab

Controller Selection
In the DDR Basic tab, use the Controller selection drop-down to select the required Controller Type.
Clock selection provides two options; Memory Clock and System Clock. If Memory Clock is selected (as shown in the previous figure), a range of values in ps is provided for the Input System Clock Period for the provided Memory Clock period. The opposite will happen if System Clock is selected. A range of values in ps is provided for the Memory Clock Period for the provided System Clock Period. The range of values provided in is determined based on the clocking architecture. For most use cases it is easier to first set the Input System Clock Period and then select the desired Memory Clock period.
  • Memory Clock Period: Enter or select the desired memory interface clock period. This clock period is half the toggle rate for DDR4 or LPDDR4/4X memory interfaces.
  • Input System Clock Period: Enter or select the desired Input System Clock Period. This clock is used to generate the clocking configuration and resulting memory interface options for the DDRMC.
  • System Clock: Three system clock options are available:
    Requires a differential clock source that must be placed on a GC input pin in any of the three XPIO banks used by the DDRMC.
    No Buffer
    Requires a differential clock source, as described for Differential, but only half of the differential pair is used by the DDRMC. The other half of the differential pair may be used as a clock source for other logic blocks.
    Uses the hsm1_ref_clk clock output from the CIPS IP. The HSM1 clock frequency and the Input System Clock frequency must be set to match each other. Use the following TCL command to enable this output port:
    set_property -dict [ list CONFIG.PS_PMC_CONFIG { PMC_HSM1_CLK_OUT_ENABLE 1 } ] [ get_bd_cells versal_cips_0 ]
  • Enable Internal Responder: Enables DDR4 or LPDDR4/4X memory device models for simulation.
    • When the Enable Internal Responder option is unchecked there are additional pins exposed at the IP integrator top level which are hooked up to the memory model provided external to the AXI NoC IP. This option enables customers to replace the AMD responder with their memory vendor model if desired.
    • When the Enable Internal Responder option is checked the AMD responder is included inside the AXI NoC IP, therefore no additional pins are added at the IP integrator level. To include the pins in simulation, search for “u_ddr_responder” and add it to the waveform window.