General Tab - General Tab - 1.1 English - PG313

Versal Adaptive SoC Programmable Network on Chip and Integrated Memory Controller 1.1 LogiCORE IP Product Guide (PG313)

Document ID
PG313
Release Date
2026-06-23
Version
1.1 English

The following figure shows the General tab of the Customize IP dialog box.

Figure 1. General Tab

Number of AXI Stream Slave Interfaces
The number of NoC ingress (NMU) ports.
Number of AXI Stream Master Interfaces
The number of NoC egress (NSU) ports.
Number of AXI Clocks
The number of AXI clocks across the set of NMU and NSU ports. Use the Inputs and Outputs tabs to define the association of clock signal with AXI port.
Number of Inter-NoC Stream Slave Interfaces
The number of Inter-NoC ingress ports.
Number of Inter-NoC Stream Master Interfaces
The number of Inter-NoC egress ports.
TDEST Width (bits)
The number of TDEST signal bits used to direct streams to the intended NoC egress (NSU) port.
TID Width (bits)
The number of data stream identifier bits that indicate different streams of data.