General Tab - 1.0 English

Versal Adaptive SoC Programmable Network on Chip and Integrated Memory Controller 1.0 LogiCORE IP Product Guide (PG313)

Document ID
PG313
Release Date
2024-05-30
Version
1.0 English

The General tab in the AXI NoC IP is used to select the number of HBM controllers and enable the rest of the options to configure the controllers. See General Tab for further details. The General tab is shown in the following figure.

Figure 1. General Tab

Controller/PHY mode
Enable both the Memory Controller and Physical Layer in the HBM subsystem.
Instantiate HBM PHYIO Control Block outside of axi_noc
Refer Configuring the HBM PHYIO Control IP to learn more about this option.
Number of Channels and Memory Size
The options under this section depend on the total available HBM memory of the selected Versal HBM series device. The total memory can be 8 GB, 16 GB, or 32 GB. The available HBM stack size can either be 8 GB or 16 GB depending on the selected device. The stack size is equally divided across the eight HBM controllers in a stack. Thus, the total memory depends on the number of controllers selected.
Starting Channel and Address
The starting channel can range from 0-15 and the address range starts from 0x40_0000_0000. This option dynamically changes depending on the number of channels or the total size of the memory.
Number of HBM AXI PL Slave Interfaces
This is the number of HBM NoC ingress (HBM_NMU) ports.
Note: In order to use the HBM controllers in the NoC IP, Number of AXI Clocks (aclk0) needs to be set to 1. This is an independent AXI clock that will be used across the set of HBM NMU and HBM NSU ports. Upon selecting HBM controllers in the General tab of the AXI NoC IP, several additional options become available for selection: Connectivity, QoS, Address Mapping, etc. using different tabs in the IP.