HBM Address Map Options Tab - 1.0 English

Versal Adaptive SoC Programmable Network on Chip and Integrated Memory Controller 1.0 LogiCORE IP Product Guide (PG313)

Document ID
PG313
Release Date
2024-05-30
Version
1.0 English

The HBM Address Map Options tab is shown in the following figure for reference.

Figure 1. HBM Address Map Options Tab

Figure 2. HBM Address Map Options Tab

The address map can be configured separately for each pseudo channel. Predefined address map settings are available in the pull-down menu, or individual address bits can be configured by selecting User Defined Address Map. Three predefined mapping choices are available as follows:

  • ROW, BANK, COLUMN, BG0
  • ROW, BANK, COLUMN, BA2
  • ROW, BANK, COLUMN

A custom mapping of address bits can be configured by selecting USER DEFINED ADDRESS MAP from the pull-down menu. When this option is selected as shown in the following figure, you can configure the ordering of the address bits by using the notations as follows:

  • RA for Row Address
  • SID for Stack ID
  • BA for Bank Address
  • BG for Bank Group
  • CA for Column Address
Note: For 8H HBM devices, the additional Bank bit is mapped to the SID bit.
Figure 3. USER DEFINED ADDRESS MAP