AXI Considerations - 1.0 English

Versal Adaptive SoC Programmable Network on Chip and Integrated Memory Controller 1.0 LogiCORE IP Product Guide (PG313)

Document ID
Release Date
1.0 English

The following table lists the AXI support and restrictions in the NoC for HBM_NMUs.

Table 1. AXI Support and Restrictions for HBM_NMUs
  Supported Unsupported/Restrictions
Interface Width 32-256 512, 1024
AxSize 8-256 512, 1024
AxBurst INCR: Support modifiable and non-modifiable transactions with restrictions Non-modifiable AXI transactions with AxSizeMaster < 0x4 and AxLenMaster > 0x0 are not supported
  WRAP: Supported with the following restrictions:
  • Transaction size can be 32B or 64B for read, 64B for write
  • AxSizeMaster limited to 2 (32-bit), 3 (64-bit), or 4 (128-bit)
AxSizeMaster not equal to 0x2, 0x3, or 0x4.

AxLenMaster not equal to 0x1, 0x3, 0x7, or 0xf.

Non-modifiable write transfers are only supported with AxSizeMaster = 0x4 and AxLenMaster = 0x3.

Non-modifiable read transfers are only supported with AxSizeMaster = 0x4 and AxLenMaster = 0x1 or 0x3.

AxCache[1] Supports INCR, WRAP, and FIXED with the restrictions stated in AxBurst Non-modifiable transfer with AxSizeSlave > 128 bits is not supported.
AxLen AXI4 - 256  
Exclusive Access Exclusive Access is limited to AxBurst == INCR

AXI conversion always sends traffic in non-modifiable INCR for both modifiable and non-modifiable. The AxCache[1] bit is not modified by the NoC.

For AXI4, with Exclusive Access size of 32B/64B/128B, the corresponding AxSizeSlave cannot be less than 2B/4B/8B respectively (that is, downsize chopping in NSU).

AXI4-Stream   Not Supported
Other Features   No support for RUSER/WUSER.

BUSER is unused.

The HBM_NMU support the AXI4 protocol. Unlike other NMUs, AXI4-Stream is not supported. Also, the HBM controller supports only INCR and WRAP type AXI burst transactions. Multiple conversions occur between a master request and a response from the AXI slave. NoC data operations are aligned on 16 byte addresses and consist of a n number of 16 byte data flits. The HBM memory, however, is structured to handle 32 bytes (256 bits) of data, 64 bits of DQ per pseudo channel with BL=4. The HBM controller has data FIFOs organized to handle even and odd pairs of 16 byte data flits from the NoC to synchronize the two bus sizes.

It is recommended to have longer bursts to gain higher performance for linear accesses. Undersized AXI writes are supported but they decrease the total system performance. Another consideration is to ensure that the AXI Write and Read addresses are aligned to the HBM physical address space and transaction size. The lower five bits of the AxADDR should be unused to ensure that accesses align to the 32-byte HBM burst boundary. This is because each individual Write or Read transaction on the HBM interface is a burst length of 4 with a DQ bus width of 64 bits, resulting in a total of 32 bytes. The AXI address space is byte aligned, so 32 bytes result in 5 bits of addressing, and these are placed at the bottom of the address bus.