Monitoring ECC Status - 1.1 English

Status Registers to Find Correctable and Uncorrectable Errors

In HW manager, under DDRMC* ecc, the following status registers can be observed:

• DDRMC_ISR_CE0_ECC0
• DDRMC_ISR_CE0_ECC1
• DDRMC_ISR_CE1_ECC0
• DDRMC_ISR_CE1_ECC1
• DDRMC_ISR_UC0_ECC0
• DDRMC_ISR_UC0_ECC1
• DDRMC_ISR_UC1_ECC0
• DDRMC_ISR_UC1_ECC1

• In the above status registers, the first 0 or 1 (CE* and UC*) indicates which half of the BLn burst contained an error, and the last 0 or 1 (ECC*) indicates the DDRMC channel number containing an error.
• When one or more errors are injected, HW will set the reg_adec15.done bit to 0x1 under DDRMC_NOC* registers.
• In persistent mode, errors will continue to be injected after the done bit is set.
• In single mode (persistent=0x0) the done bit must be cleared to enable another single error injection.
• During correctable error detection DRAM will be scrubbed.
• During uncorrectable error detection SLVERR Read response will be returned to the host.

Decoding DDRMC ECC Errors

For information about how to decode DDRMC ECC Errors, refer to AR 000034749.