Read DQ Per-Bit Deskew and Centering (Simple) - 1.0 English

Versal Adaptive SoC Programmable Network on Chip and Integrated Memory Controller 1.0 LogiCORE IP Product Guide (PG313)

Document ID
PG313
Release Date
2024-05-30
Version
1.0 English

Calibration Overview

Read Per-Bit DQ Deskew

Because Write Centering calibration has not yet been performed, write operation cannot be carried out properly. Data pattern 10101010 stored in mode register (MPR0) of DRAM is read back to back for performing per bit deskew. The figure shows the pattern read from MPR0 of DRAM.

Figure 1. Repeating Pattern Read from MPR0

At the start of deskew, PDQS and NDQS of all the nibbles are delayed together until the PDQS of each nibble finds valid stable region for each bit of its nibble once. Only the rising edge data is checked for correctness. The falling edge comparison is thrown away to allow for extra delay on the PDQS/NDQS relative to the DQ. The final delay tap applied for delaying PDQS and NDQS together is stored as BRAM_RDDQ_QTR_DESKEW_NIBBLE*.

The figure shows the initial alignment of PDQS/NDQS with DQ bits of the nibble.

Figure 2. Per-Bit Deskew – Initial Relationship Example

The figure shows the alignment of PDQS/NDQS with DQ bits of the nibble after detecting valid stable region for all DQ bits in the nibble once.

Figure 3. Per-Bit Deskew – Detecting Valid Stable Region

After detecting valid stable region for all DQ bits in the nibble once. All DQ bits in the nibble are delayed in parallel until valid stable region to noise region crossing is detected on their PDQS sampling. The final DQ IDELAY value from deskew is stored at BRAM_RDDQ_IDELAY_FINAL_BIT*. The figure shows the alignment of PDQS/NDQS with DQ bits in the nibble after detecting transition from valid stable region to noise region.

Figure 4. Per-Bit Deskew – Detecting Valid Stable Region to Noise Region Crossing

CAL_ERROR Decode for Read Per-Bit DQ Deskew Calibration

The status of Read Per-Bit DQ Deskew can also be determined by decoding the CAL_ERROR result according to the following table.

Table 1. CAL_ERROR Decode for Read Per-Bit DQ Deskew Calibration
Error Code Description Recommended Debug Step
0xC No valid data found for a given bit in the nibble by incrementing PQTR/NQTR IDELAY together using step size of 1 tap. Check the pinout and look for any STUCK-AT-BITs, check vrp resistor, VREF resistor. Check BRAM_BISC_PQTR, BRAM_BISC_NQTR for starting offset between rising/falling clocks.
0xD No valid data found for a given bit in the nibble by incrementing DQ IDELAY using step size of 1 tap. Check the dbg_rd_data, dbg_rd_data_cmp, and dbg_expected_data signals in the ILA. Check the pinout and look for any STUCK-AT-BITs, check vrp resistor, VREF resistor. Check BRAM_BISC_PQTR, BRAM_BISC_NQTR for starting offset between rising/falling clocks.
0xE Noise region not found for a given bit in the nibble by incrementing DQ IDELAY using step size of 10 taps. Check for a mapping issue. This usually implies a delay is not moving when it should. Check the connections going to the XPHY and ensure the correct RIU is selected based on the byte being adjusted.
0xF Noise region not found for a given bit in the nibble by incrementing DQ IDELAY using step size of 1 tap. Check for a mapping issue. This usually implies a delay is not moving when it should. Check the connections going to the XPHY and ensure the correct RIU is selected based on the byte being adjusted.

Read DQS Centering (Simple/MPR)

After the data is deskewed, the PQTR/NQTR delays need to be adjusted to center in the aggregate data valid window for a given nibble. The DRAM MPR register is used to provide the data pattern for centering. Therefore, the pattern changes each bit time and does not rely on being written into the DRAM first, eliminating some uncertainty. Gaps in the reads to the DRAM are used to stress the initial centering to incorporate the effects of ISI on the first DQS pulse as shown in the figure.

Figure 5. Gap between MPR Read

Given that the PHY has two capture strobes PDQS/NDQS that need to be centered independently yet moved together, calibration needs to take special care to ensure the clocks stay in a certain phase relationship with one another.

The data and PDQS/NDQS strobe delays start with the value found during DQ per bit deskew. Data is first delayed with IDELAY such that both the PDQS and NDQS clocks start out just to the left of the data valid window for all bits in a given nibble, so the entire read window can be scanned with each clock (see figure below, BRAM_DQ_IDELAY_FINAL_BIT*). Scanning the window with the same delay element and computing the center with that delay element helps to minimize uncertainty in tap resolution that might arise from using different delay lines to find the edges of the read window.

Figure 6. Delay DQ Thus PDQS and NDQS in Failing Region

At the start of training, the PDQS/NDQS and data are roughly edge aligned. During deskew the aggregate edge for both PDQS/NDQS is found while you want to find a separate edge for each clock.

After making sure both PDQS/NDQS start outside the data valid region, the clocks are incremented to look for the passing region (see the following figure). Rising edge data is checked for PDQS while falling edge data is checked for NDQS, with a separate check to indicate where the passing region/falling region is for each clock.

Figure 7. PDQS and NDQS Delayed to Find Passing Region (Left Edge)

When searching for the edge, a minimum window size of 15 is used to guarantee the noise region has been cleared and the true edge is found. The PQDS/NDQS delays are increased past the initial passing point until the minimum window size is found before the left edge is declared as found. If the minimum window is not located across the entire tap range for either clock, an error is asserted.

After the left edge is found (BRAM_RDDQ_PQTR_LEFT_NIBBLE*, BRAM_RDDQ_PQTR_LEFT_NIBBLE*), the right edge of the data valid window can be searched starting from the left edge + minimum window size. Again, the PQTR/NQTR delays are incremented together using step size of 10 taps and checked for error independently to keep track of the right edge of the window. Because the data from the PDQS domain is transferred into the NDQS clock domain in the XPHY, the edge for NDQS is checked first, keeping track of the results for PDQS along the way (see the following figure).

When the NDQS edge is located, a flag is checked to see if the PDQS edge is found as well. If the PDQS edge was not found, the PQTR delay continues to search for the edge, while the NQTR delay stays at its right edge (BRAM_RDDQ_PQTR_RIGHT_FCRSE_NIBBLE*, BRAM_RDDQ_NQTR_RIGHT_FCRSE_NIBBLE*).

The PQTR/NQTR delays are decremented together using step size of 1 tap to ensure a minimum window size of 15 is detected to guarantee the noise region has been cleared and the true right edge is found (BRAM_RDDQ_PQTR_RIGHT_NIBBLE*, BRAM_RDDQ_NQTR_RIGHT_NIBBLE*).

Figure 8. PDQS and NDQS Delayed to Find Failing Region (Right Edge)

After both rising and falling edge windows are found, the final center point is calculated based on the left and right edges for each clock. The final delay for each clock (BRAM_RDDQ_PQTR_FINAL_NIBBLE*, BRAM_RDDQ_NQTR_FINAL_NIBBLE*) is computed by: left + ((right – left) / 2).

CAL_ERROR Decode for Read DQS Centering Calibration

The status of Read DQS Centering can also be determined by decoding the CAL_ERROR result according to the following table.

Table 2. CAL_ERROR Decode for Read DQS Centering Calibration
Error Code Description Recommended Debug Step
0x10 Noise region not found for a given bit in the nibble by incrementing DQ IDELAY. Check for a mapping issue. This usually implies a delay is not moving when it should. Check the connections going to the XPHY and ensure the correct RIU is selected based on the byte being adjusted.
0x11 Could not find the left edge of valid data window by incrementing PQTR/NQTR IDELAY together. Check for a mapping issue. This usually implies a delay is not moving when it should. Check the connections going to the XPHY and ensure the correct RIU is selected based on the byte being adjusted.
0x12 Could not find the right edge of valid data window by decrementing PQTR/NQTR IDELAY together. Check for a mapping issue. This usually implies a delay is not moving when it should. Check the connections going to the XPHY and ensure the correct RIU is selected based on the byte being adjusted.
0x13 Negative sanity check failed. Check CAL_ERROR_BIT_*_*,CAL_ERROR_DATA_NIBBLE_*_*,CAL_ERROR_PHY_NIBBLE_*_* XSDB registers to determine which nibbles/bits failed. Check margin found during previous stages of calibration for the given byte that failed.
0x14 Positive sanity check failed. Check CAL_ERROR_BIT_*_*,CAL_ERROR_DATA_NIBBLE_*_*,CAL_ERROR_PHY_NIBBLE_*_* XSDB registers to determine which nibbles/bits failed. Check margin found during previous stages of calibration for the given byte that failed.
Table 3. Read DQ Per-Bit Deskew and Centering (Simple) Registers
Register Name Quantity Description
Fx_RDDQ_QTR_DESKEW Nibble Coarse taps needed to find the valid region of rising edge clock.
Fx_RDDQ_IDELAY_FINAL DQ bit Final IDELAY values for each data bit in the read path.
Fx_RDDQ_PQTR_LEFT Nibble Left edge of valid window for rising edge clock.
Fx_RDDQ_NQTR_LEFT Nibble Left edge of valid window for falling edge clock.
Fx_RDDQ_PQTR_RIGHT_FCRSE Nibble Valid-to-noise coarse tap value for rising edge clock.
Fx_RDDQ_NQTR_RIGHT_FCRSE Nibble Valid-to-noise coarse tap value for falling edge clock.
Fx_RDDQ_PQTR_RIGHT Nibble Right edge of valid window for rising edge clock.
Fx_RDDQ_NQTR_RIGHT Nibble Right edge of valid window for falling edge clock.
Fx_RDDQ_PQTR_FINAL Nibble Final delay value for rising edge clock strobe.
Fx_RDDQ_NQTR_FINAL Nibble Final delay value for falling edge clock strobe.