1x48 Component Interface (Flipped) - 1.0 English

Versal Adaptive SoC Programmable Network on Chip and Integrated Memory Controller 1.0 LogiCORE IP Product Guide (PG313)

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1.0 English
Figure 1. Connections for a 1x32 (or x48) with ECC LPDDR4/4x Interface

Nibble utilization for 1x48 interface (or 1x32 with ECC) in the flipped configuration is shown in the following figure. DQ indicates data nibbles, AC indicates Address/Command/Control nibbles, sys_clk indicates a nibble comprising the Reference Clock pair, RESET_n, and ALERT_n signals. Note that the AC nibbles for the ECC device are on nibbles 6 and 7 in the first Bank and DQ nibbles for the ECC device are on nibbles 4 and 5 in the first Bank and nibble 0 and 1 in the second Bank. For a 1x32 interface all nibbles in the first Bank and nibbles 0, 1, 4, 5, and 8 in the second Bank would be free.

Important: The nibble utilization figure is based on the fixed pinout output by Vivado for this configuration.
Figure 2. Nibble Utilization for 1x48 Component Interface (Flipped)