Calibration Stages - 1.1 English

The following figure shows the calibration steps for DDR4 designs.

Refer to the Calibration Stage window in the Vivado Hardware Manager to identify if there is a stage of calibration that has failed. The software utilizes the CAL_SEQ_STATUS and CAL_POINTER registers to populate the table.

There are 64 CAL_SEQ_STATUS registers which contain the calibration stage codes as well as the status of each calibration stage. Calibration starts with CAL_SEQ_STATUS_0. There are 64 registers allowing for a maximum of 64 stages, but in practice only a subset is utilized.

The CAL_POINTER register indicates the current status and stage of calibration. By the time the Hardware Manager refreshes these registers it is likely that calibration has already completed, so you should not expect to see it change values. In the event of a calibration error, it will point at the stage where the error occurred. In the event of an error during calibration, the Vivado Hardware Manager will display additional information regarding the reason for failure.

The encoding of the CAL_SEQ_STATUS and CAL_POINTER register is shown in the following table.

If calibration has completed successfully, CAL_POINTER Status will be b'110 (Calibration stage completed successfully) and the Stage will be x3f (CAL_DONE). The concatenated value will be x1bf. If calibration encounters an error, the Status will be b'111 (Calibration stage failed) and the Stage will indicate the failing stage.

If a calibration error occurs, Hardware Manager extracts the error code from the register CAL_ERROR. The error codes can be decoded from Table 2.

If there is a bit or a nibble number given in the error message, it refers to the physical pin/nibble number given in the package file for the I/O triplet containing the memory controller.

There are three IO Banks in a triplet. The first IO bank contains nibbles 0..8, the next contains 9..17, and the last 18..26.