The memory controller will periodically read the oscillator values from the DRAM and if enough variation is detected, adjust the write latency values to compensate. This adjustment is done to one rank while activity is being performed on the other.
Register Name | Quantity | Description |
---|---|---|
LP4DQSOSCTRACK_WLDLYRNK0_FINE | Nibble | Fine taps for WLDLYRANK0 |
LP4DQSOSCTRACK_WLDLYRNK0_FINE_MAX | Nibble | Largest value of fine taps for WLDLYRANK0 since calibration completed |
LP4DQSOSCTRACK_WLDLYRNK0_FINE_MIN | Nibble | Smallest value of fine taps for WLDLYRANK0 since calibration completed |
LP4DQSOSCTRACK_WLDLYRNK1_FINE | Nibble | Fine taps for WLDLYRANK1 |
LP4DQSOSCTRACK_WLDLYRNK1_FINE_MAX | Nibble | Largest value of fine taps for WLDLYRANK1 since calibration completed |
LP4DQSOSCTRACK_WLDLYRNK1_FINE_MIN | Nibble | Smallest value of fine taps for WLDLYRANK1 since calibration completed |