LPDDR4 OSC Tracking - 1.1 English

Versal Adaptive SoC Programmable Network on Chip and Integrated Memory Controller 1.1 LogiCORE IP Product Guide (PG313)

Document ID

PG313

Release Date

2024-11-13

Version

1.1 English

The memory controller will periodically read the oscillator values from the DRAM and if enough variation is detected, adjust the write latency values to compensate. This adjustment is done to one rank while activity is being performed on the other.

Table 1. LPDDR4 OSC Tracking Registers
Register Name	Quantity	Description
LP4DQSOSCTRACK_WLDLYRNK0_FINE	Nibble	Fine taps for WLDLYRANK0
LP4DQSOSCTRACK_WLDLYRNK0_FINE_MAX	Nibble	Largest value of fine taps for WLDLYRANK0 since calibration completed
LP4DQSOSCTRACK_WLDLYRNK0_FINE_MIN	Nibble	Smallest value of fine taps for WLDLYRANK0 since calibration completed
LP4DQSOSCTRACK_WLDLYRNK1_FINE	Nibble	Fine taps for WLDLYRANK1
LP4DQSOSCTRACK_WLDLYRNK1_FINE_MAX	Nibble	Largest value of fine taps for WLDLYRANK1 since calibration completed
LP4DQSOSCTRACK_WLDLYRNK1_FINE_MIN	Nibble	Smallest value of fine taps for WLDLYRANK1 since calibration completed