NMU128 (Low Latency) - 1.0 English

Versal Adaptive SoC Programmable Network on Chip and Integrated Memory Controller 1.0 LogiCORE IP Product Guide (PG313)

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1.0 English

The NMU128 is optimized for the low latency requirements of hardened blocks such as the CIPS. The NMU128 has a fixed 128-bit AXI data width. It does not support the AXI4-Stream protocol and does not support master-defined destination IDs. Otherwise, it supports all of the features of the NMU512.