NMU128 (Low Latency) - NMU128 (Low Latency) - 1.1 English

NMU128 (Low Latency) - NMU128 (Low Latency) - 1.1 English - PG313

Versal Adaptive SoC Programmable Network on Chip and Integrated Memory Controller 1.1 LogiCORE IP Product Guide (PG313)

Document ID

PG313

Release Date

2026-06-23

Version

1.1 English

Use NMU128 for hardened blocks, such as CIPS, to meet low-latency requirements. The NMU128 has a fixed 128-bit AXI data width. It does not support the AXI4-Stream protocol and does not support master-defined destination IDs. Otherwise, it supports all of the features of the NMU512.