Clamshell Topology - 1.0 English

Versal Adaptive SoC Programmable Network on Chip and Integrated Memory Controller 1.0 LogiCORE IP Product Guide (PG313)

Document ID
PG313
Release Date
2024-05-30
Version
1.0 English

Clamshell topology saves the component area by placing them on both sides (top and bottom) of the board to mimic the address mirroring concept of multi-rank DIMMs. Address mirroring improves the signal integrity of the address and control ports while also making PCB routing easier. The clamshell topology is only supported for DDR4 single-rank components. The Clamshell option is available on the DDR Memory tab of the NoC configuration GUI.

The components are split into two categories called non-mirrored and mirrored. One additional chip select signal is added to the design for the mirrored components as shown in the following figure. The figure in this example shows two CK pairs in addition to two chip select signals because the load on one CK pair would be greater than nine die with five single-rank, x16 DDP devices. Greater than nine loads on a CK pair will result in signal integrity issues. Refer to the Versal Adaptive SoC PCB Design User Guide (UG863) for details on PCB design guidelines.

Note: With DDR4 clamshell interfaces, it is required that CS0 and Byte0 (DQ[7:0]) be associated with the non-mirrored devices in order for calibration to complete successfully.
Note: Simulation for clamshell configuration is currently not supported.
Figure 1. Clamshell Configuration Example