DDR Memory Options Tab - 1.0 English

Versal Adaptive SoC Programmable Network on Chip and Integrated Memory Controller 1.0 LogiCORE IP Product Guide (PG313)

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1.0 English

The DDR Memory Options tab is shown in the following figure for reference

Figure 1. DDR Memory Options Tab 1/2

Figure 2. DDR Memory Options Tab 2/2

DDR Memory Options
Select device type, speed bin, base component width and memory device width.
Device Type
Select from the following memory form factor options:
  • Components
  • UDIMMs
  • RDIMMs
Speed Bin (Monolithic/3DS)
Options to select a JEDEC supported speed bin for a selected DDR4 or LPDDR4/4X SDRAM controller type. For example, if a selection of x8 and 2 ranks is made then the tool infers it as Dual-Die Package (DDP). When DDR4 is selected for the Controller Type on the DDR Basic tab, the second half of the pull-down has 3DS devices.
Base Component Width
The width of the base die on a selected Memory Device type.
Memory Device Width
DDR4 only. This option is applicable only for Component Memory Devices with a base component width of x8. Use this option to differentiate between a x8 device vs. a x16 with two x8 die.
Memory Density Parameters
Row Address Width
Consult the memory data sheet addressing table.
Bank Group Width
(DDR4 only) Automatically calculated.
Bank Address Width
Automatically calculated.
Number of Channels
One or two independent sub-channels within a single memory controller.
Data width
The data width per channel for selected memory configuration.
Select the number of ranks based on the memory topology.
Stack Height
(DDR4 only) Select the stack height of the 3DS memory device.
(DDR4 only) Set the number of slots for the RDIMM/LRDIMM topology.
Number of Memory Clocks
(DDR4 only) Set to 2 when using more than four DDR4 DDP deep components at or above 1866 Mbps. For details refer to DDR4 Dual CK Configuration.
Select to enable ECC for a selected memory configuration.
Write DBI/Read DBI
Data bus inversion selection on memory and controller side. The Write Data Mask (DM) option is also available in this drop down when applicable.
Channel Interleaving
The DDRMC supports interleaving across two memory channels by automatically chopping AXI requests into interleave block-sized sub-requests and alternatively sending sub-requests to each of the two channels. Channel Interleaving in a single controller does not affect chopping.
DRAM Command/Address Parity
(DDR4 only) Check this option to enable Command/Address Parity.
CA Mirror (DDR4 only)
(DDR4 only) Enables address mirroring as required by memory topology.
(DDR4 only) Enables Clamshell topology when selected. For details refer to Clamshell Topology.
Note: Options 10, 13, 14, and 15 are supported in hardware only and are not reflected in simulations.
LP4 Pin Efficient
(LPDDR4/X Only): Reduces the number of required pins. This option is limited to single rank memory topologies.
Future Expansion for PCB Design (set per Interleaved MC)
Multiple options are available based on the memory configuration selection. Refer to Pinout Options for Future Expansion. Following are the available options:
Gives the standard pin out for a selected memory configuration.
Ranks Expansion
Supports the selected memory configuration and creates pins for future rank expansion.
Slot Rank and Stack Height Expansion
Supports the selected memory configuration and creates pins for future expansion.
CLK Expansion
Set to 2 when using more than four DDR4 DDP deep components at or above 1866 Mbps.
Important: When an Expansion option is selected the tools will only generate the additional pin sites based on the current configuration. For example if future designs can require a Dual Rank DDR4 topology, then set the Ranks option to 2 so those pins are generated in the pinout.
Flipped Pinout (set per Interleaved MC)
MC0 Flipped Pinout: Flipping reverses the ordering of all the nibbles within the triplet of banks. Some of the nibbles end up being 'shadowed' by hardened blocks on the die. Nibbles that are shadowed can only be used by the DDRMC. These cannot be re-purposed. For detailed information refer to Pinout Rules.
Timing Parameters
Default values are based on the JEDEC specification per selected speed bin and operating point.
Mode Register Settings
CAS latency(nCK)
The CAS latency options for a selected memory configuration.
CAS Write latency(nCK)
The CAS Write latency for a selected memory configuration.
Operating Temperature
Available only for LPDDR4 SDRAM. Two options are available; Standard or High. Selecting High derates certain timing parameters.

The Timing Parameters selections under DDR4 Memory Options need to be selected from the memory data sheet based on the required memory speed bin. Default values are based on the JEDEC specification per selected speed.