Refresh - 1.0 English

Versal Adaptive SoC Programmable Network on Chip and Integrated Memory Controller 1.0 LogiCORE IP Product Guide (PG313)

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1.0 English

The HBM controller supports three Refresh modes, and one external Refresh mode:

All Bank Refresh
All banks are refreshed together.
All Bank Refresh with Deficit Mode
Refreshes can be skipped up to eight times if there are transactions in the queue. When the transaction queue is empty, refreshes can be performed repeatedly to replace skipped refreshes, or issued in advance of future refresh requirements.
Single Bank Refresh
Banks are refreshed separately which can improve efficiency depending on the address access pattern.
Global Refresh Pin
The global refresh pin is available for designs where you want to manually control the timing of the refresh operations from the FPGA fabric. Every HBM channel has its own external global refresh signal available for use from the fabric. Multiple HBM channels can be ganged together to create a wider data bus, in which case the associated external global refresh signals can be used to synchronize the refresh across the channels, thus aiding in generating tandem read data across the channels and minimizing external data buffering requirements. In this use case, the refresh type will be All Bank Refresh to both Pseudo Channels. When the User Refresh pin is used the controller will not issue any refresh commands on its own. All memory refresh operations are the responsibility of the user.

This is an asynchronous active-Low pin and has a pulse width minimum of 8 ns. The time from assertion to refresh execution is less than 50 ns + 26 memory controller clock cycles (½ HBM frequency).

When an HBM controller is in Self-Refresh, refresh operation requests from the Global Refresh pin are ignored.