Integrated HBM Controller - 1.0 English

Versal Adaptive SoC Programmable Network on Chip and Integrated Memory Controller 1.0 LogiCORE IP Product Guide (PG313)

Document ID
PG313
Release Date
2024-05-30
Version
1.0 English

The Versal HBM family contains up to two HBM2E memory stacks of 8 or 16 GB each and an integrated AXI HBM controller for each memory channel (8) in the stack. Each controller is divided into two semi-independent 64-bit pseudo channels which addresses a dedicated portion of the HBM. Eight HBM controllers in each stack contains 16 of these pseudo channels, making the total stack data-width 1024 bits. Each pseudo channel can address 512 MB (for an 8 GB stack) or 1 GB (for a 16 GB stack). The controller and PHY operate at up to 1600 MHz for a transfer rate of 3200 MT/s. With 128 bits per channel, eight channels per stack, and two stacks in most devices, this yields a maximum throughput of 819 GB/s.