AXI Support and Restrictions - 1.1 English

Versal Adaptive SoC Programmable Network on Chip and Integrated Memory Controller 1.1 LogiCORE IP Product Guide (PG313)
Document ID
PG313
Release Date
2024-11-13
Version
1.1 English

AXI support and restrictions in the NoC are summarized in the following table.

Table 1. AXI Support
  Supported Not Supported/Restrictions
Interface Width 32-512 1024
AxSize 8-512 1024
AxBurst INCR: Support modifiable and non-modifiable transactions with restrictions  
WRAP: Supported with the following restrictions:
  • Transaction size can be 32B or 64B for read, 64B for write
  • AxSizeMaster limited to 2 (32-bit), 3 (64-bit), or 4 (128-bit)
 AxSizeMaster not equal to 2, 3, or 4

AxSizeMaster is 4 and InterfaceWidthSlave is less than 4
FIXED: Supported with the following restrictions:
  • AxSizeMaster <= AxSizeNoC(4)
  • AxSizeMaster <= InterfaceWidthSlave
  • Transaction is not modified (no upsize or downsize) from the NoC Master to the NoC Slave
  
AxCache[1] Supports INCR, WRAP, and FIXED with the restrictions stated in AxBurst Non-modifiable transfer with AxSizeSlave > 128 is not supported
AxLen AXI4 - 256  
Exclusive Access Exclusive Access is limited to AxBurst == INCR


For DDR, AxLenMaster = 1-flit and AxSizeMaster <= 4 (128-bit), NMU would send the AxSizeMaster instead of the AxSize of 4 (128-bit) for modifiable and non-modifiable.

For DDR, AxLenMaster > 1-flit, NMU would send upsized (packed) AxSize of 4 (128-bit) for modifiable and non-modifiable. Read over-fetch is expected.

For non-MC slave, AXI conversion always sends traffic in non-modifiable INCR for both modifiable and non-modifiable. The AxCache[1] bit is not modified by the NoC.

For AXI4, with Exclusive Access size of 32B/64B/128B, the corresponding AxSizeSlave cannot be less than 2B/4B/8B respectively (i.e., downsize chopping in NSU).

  
AXI4-Stream 32-bit and 64-bit interface widths are unsupported in the NMU and NSU.

Support and behave as modifiable Write with Interface WidthMaster == AxSizeMaster; Interface WidthSlave == AxSizeSlave;

Support 6-bit TID

Support 10-bit TDEST

 TKEEP is supported.

TSTRB is not supported.
TUSER is not supported.
NMU can switch TID (interleave on TID) or TDEST (interleave on TDEST) only if:

  1. The current TID/TDEST has finished sending a multiple of 64B data
  2. The transaction is ending with TLAST = 1
Other features  


No support for RUSER for Read Response
No support for TSTRB for AXI Stream
No support for WUSER and BUSER ports as they are unused in the NoC packet protocol