Memory Initialization

Memory Initialization - 1.1 English

Versal Adaptive SoC Programmable Network on Chip and Integrated Memory Controller 1.1 LogiCORE IP Product Guide (PG313)

Document ID

PG313

Release Date

2024-11-13

Version

1.1 English

The PHY issues commands to load the DDR4 Mode registers with values defined in the user IP settings. There are no debug registers associated with this calibration stage.