HBM_NMU - 1.0 English

Versal Adaptive SoC Programmable Network on Chip and Integrated Memory Controller 1.0 LogiCORE IP Product Guide (PG313)

Document ID
PG313
Release Date
2024-05-30
Version
1.0 English

The HBM_NMU available on Versal HBM series connects the PL fabric array to the HBM controllers via a set of low latency NoC paths. The addition of these localized HBM_NMUs is necessary to fully use the HBM bandwidth by providing direct access from PL to the HBM. The HBM_NMUs are distributed evenly across the PL for ease of timing closure. The AXI data width of the HBM_NMU is configurable from 32 bits to 256 bits. The HBM_NMU does not support the AXI4-Stream protocol. The Read Reorder buffer is larger than other NMUs with 64 entries of 64 bytes per entry instead of 32 bytes per entry. The HBM_NMUs support three different Write Ordering schemes.

Note: The AXI transactions with AxSize < 4 and AxLen > 0 originating in fabric and targeted for HBM memory should be initiated as modifiable transactions by setting AxCache[1].