Simulation Settings - 1.0 English

Versal Adaptive SoC Programmable Network on Chip and Integrated Memory Controller 1.0 LogiCORE IP Product Guide (PG313)

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1.0 English

In the Flow Navigator click Simulation > Simulation Settings. This opens the Project Settings menu on the Simulation tab as shown.

Figure 1. Simulation Settings

Set the Target simulator to Vivado Simulator.

Note: The wrapper created above is now the Simulation top module name.

SystemC Simulation of the NoC

By default, Run Simulation uses a System Verilog behavioral model of the NoC and DDRMC. Vivado has the ability to use a much faster SystemC model of the NoC and DDRMC. To enable SystemC modeling, every instance of the AXI NoC and AXIS NoC needs to have the property SELECTED_SIM_MODEL set to tlm. The following figure shows changing the selected sim model to System C by setting it to tlm (by default, the value is set to rtl). Note that the SystemC model is much faster but less accurate compared to the System Verilog model. The SystemC model can be used to verify functionality, but for modeling performance System Verilog should be used.

The Tcl command to select a simulation model is as follows. Set it to tlm for SystemC or rtl for System Verilog.

set_property SELECTEC_SIM_MODEL tlm [get_bd_cells/axi_noc_0]
Figure 2. Simulation Model Setting
Note: TLM model supports simulation only with Internal Responder.

Error Messages

The NoC / DDRMC IPs contains three types of error messages:

  • Fatal
  • Error
  • Warning

The error messages can be managed by adding the following runtime arguments from the following table, either in the script or in more_options section of simulation tab of the corresponding simulator.

Table 1. Runtime Arguments
Desired Action Argument
Convert Error to Warning VERBOSITY_ERR_TO_WARN
Disable warning message IGNORE_WARNING