HBM Configuration Tab - 1.0 English

Versal Adaptive SoC Programmable Network on Chip and Integrated Memory Controller 1.0 LogiCORE IP Product Guide (PG313)

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1.0 English

Enabling an HBM controller will add the HBM Configuration tab. The HBM Configuration tab is shown in the following figure.

Figure 1. HBM Configuration Tab

Configure all Channels to Same Value?
Select Yes to configure all memory controllers to use the same settings. Select No to allow memory controller options to be configured independently.
HBM Clock
Select between internal clock (HSM0) or the external clock pins for the HBM. If the external clock source is selected, the user needs to select the IO standard for the reference clock. The supported IO standards are LVDS for differential clock and LVCMOS for Single-ended clock.
HBM Memory Frequency for Stack
Select the operating frequency of the HBM. HBM operates in Double data rate mode and hence the actual data rate is double the frequency set in this option.
HBM Reference Frequency for Stack
Select the frequency provided to the reference clock port. Internal clock has a range of 100-200 MHz and the external clock has a range of 100-500 MHz.
Configure Channels
Clicking this button will launch a Configure Channels dialog box. The new dialog box has three tabs:
  • HBM Address Map Options
  • HBM Refresh and Power Savings Options
  • HBM Reliability Options
Enable DFI_Clock/2 port
This creates an output clock port that has a frequency equal to the HBM clock/4.