Calibration Overview
The final stage of Write DQS-to-DQ/DBI centering that is completed before normal operation is repeating the steps performed during Write DQS-to-DQ/DBI centering but with a difficult/complex pattern. The purpose of using a complex pattern is to stress the system for SI effects such as ISI and noise while calculating the write DQS center and write DQ positions. This ensures the write center position can reliably capture data with margin in a true system.
- Turn on DBI on the write path, turn off DM on the write path, and DBI on the read path (MRS setting in the DRAM and fabric switch).
- Write complex pattern into the DRAM memory and read back.
- Find the left margin of the write data window by incrementing each DQ ODELAY and DBI ODELAY(if enabled) by step size of 10 taps until invalid data pattern is detected. Once completed, decrement each DQS ODELAY and DBI ODELAY (if enabled) by step size of 10 taps. At the end of this stage, left margin value is saved as BRAM_WRCMPLX_LEFT_MARGIN_FCRSE.
- Find the left margin of the write data window again by incrementing each DQ ODELAY and DBI ODELAY (if enabled) by one fine tap at a time until invalid data pattern is detected. At the end of this stage, left margin values are saved as BRAM_WRCMPLX_LEFT_MARGIN.
- Find the right margin of the write data window by incrementing DQS ODELAY by step size of 10 taps until invalid data pattern is detected. At the end of this stage, right margin values are saved as BRAM_WRCMPLX_RIGHT_MARGIN_FCRSE.
- Find the right margin of the write data window by incrementing DQS ODELAY by one fine tap at a time until invalid data pattern is detected. At the end of this stage, right margin values are saved as BRAM_WRCMPLX_RIGHT_MARGIN.
- Calculate the center tap location for the DQS ODELAY, based on
left margin and right margin. Final DQS, DQ and DBI ODELAY values are calculates
as:
- Right Margin > Left Margin
- DQS ODELAY = initial ODELAY - [(Left Margin + Right Margin) / 2
- DQ ODELAY = No change
- DBI ODELAY = No change
- Left Margin > Right Margin
- DQS ODELAY = No change
- DQ ODELAY = initial ODELAY + [(Left Margin - Right Margin) / 2]
- DBI ODELAY = initial ODELAY + [(Left Margin - Right Margin) / 2]
- Right Margin > Left Margin
CAL_ERROR Decode for Write DQS to DQ/DBI Centering Complex
The status of Write DQS to DQ/DBI Centering Complex can also be determined by decoding the CAL_ERROR result according to the following table.
Error Code | Description | Recommended Debug Step |
---|---|---|
0x37 | Could not find the left edge of valid data window by incrementing DQ and DBI ODELAY (if enabled) together using step size of 10 taps. | Check for a mapping issue. This usually implies a delay is not moving when it should. Check the connections going to the XPHY and ensure the correct RIU is selected based on the byte being adjusted. |
0x38 | Could not find the left edge of valid data window by incrementing DQ and DBI ODELAY (if enabled) together using step size of 1 tap. |
Check for a mapping issue. This usually implies a delay is not moving when it should. Check the connections going to the XPHY and ensure the correct RIU is selected based on the byte being adjusted. |
0x39 | Could not find the right edge of valid data window by incrementing DQS ODELAY using step size of 10 taps. | Check for a mapping issue. This usually implies a delay is not moving when it should. Check the connections going to the XPHY and ensure the correct RIU is selected based on the byte being adjusted. |
0x3A | Could not find the right edge of valid data window by incrementing DQS ODELAY using step size of 1 tap. | Check for a mapping issue. This usually implies a delay is not moving when it should. Check the connections going to the XPHY and ensure the correct RIU is selected based on the byte being adjusted. |
0x3B | Positive sanity check failed. | Check CAL_ERROR_BIT_*_*, CAL_ERROR_DATA_NIBBLE_*_*, CAL_ERROR_PHY_NIBBLE_*_* XSDB registers to determine which nibbles/bits failed. Check margin found during previous stages of calibration for the given byte that failed. |
0x3C | Could not find the right edge of valid data window by decrementing DQ ODELAY using step size of 10 taps. | Check for a mapping issue. This usually implies a delay is not moving when it should. Check the connections going to the XPHY and ensure the correct RIU is selected based on the byte being adjusted. |
0x3D | Could not find the right edge of valid data window by decrementing DQ ODELAY using step size of 1 taps. | Check for a mapping issue. This usually implies a delay is not moving when it should. Check the connections going to the XPHY and ensure the correct RIU is selected based on the byte being adjusted. |
0x3E | Positive sanity check 1 failed. | Check CAL_ERROR_BIT_*_*, CAL_ERROR_DATA_NIBBLE_*_*, CAL_ERROR_PHY_NIBBLE_*_* XSDB registers to determine which nibbles/bits failed. Check margin found during previous stages of calibration for the given byte that failed. |
0x3F | Write complex read DQS oscillator value to be 0. | |
0x40 | Write complex computed tDQS2DQ value to be out of range. |
Register Name | Quantity | Description |
---|---|---|
Fx_WRCMPLX_RIGHT_MARGIN_FCRSE | Byte | Taps of right side margin - 10 tap increments |
Fx_WRCMPLX_RIGHT_MARGIN | Byte | Taps of right side margin |
Fx_WRCMPLX_LEFT_MARGIN_FCRSE | Byte | Taps of left side margin - 10 tap increments |
Fx_WRCMPLX_LEFT_MARGIN | Byte | Taps of left side margin |
Fx_WRCMPLX_ODLY_DQS_FINAL | Byte | Final delay value for DQS |
Fx_WRCMPLX_ODLY_DQ_FINAL | DQ Pin | Final delay value for DQ bit |
Fx_WRCMPLX_ODLY_DBI_FINAL | DBI Pin | Final delay value for DBI bit |