Error Correction Code - 1.0 English

Versal Adaptive SoC Programmable Network on Chip and Integrated Memory Controller 1.0 LogiCORE IP Product Guide (PG313)

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1.0 English

Eight bits of Single Error Correct and Dual Error Detect (SECDED) Error Correction Code can be calculated with every burst of write data. This is stored in the HBM and can be checked during read operations. In the event of an ECC error, it will be logged and optionally an interrupt will be triggered. Reads that are correctable will be corrected with no impact to performance. The HBM Controller can be configured to write back corrected values to the HBM, with an impact to efficiency.

  1. ECC and Data Mask cannot be used concurrently.
  2. If ECC is not used, the ECC memory space cannot be used to store extra data.