Slave Bridge Registers Limitations - 3.4 English

Versal Adaptive SoC CPM DMA and Bridge Mode for PCI Express Product Guide (PG347)

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3.4 English

The Register Space mentioned in this document can also be accessible through the AXI4 Memory Mapped Slave interface. All accesses to these registers will be based on the following AXI Base Addresses:

  • For QDMA registers: Base Address = 0x6_1000_0000
  • For Bridge registers: Base Address = 0x6_0000_0000

The offsets within each register space are the same as listed for the PCIe BAR accesses.

Please make sure that all transactions targeting these register spaces have AWCACHE[1] and ARCACHE[1] set to 1’b0 (Non-Modifiable) and only access it in 4 Bytes transactions.

  • All transactions originating from Programmable Logic (PL) region, must have an AXI Master that sets AxCACHE[1] = 1’b0 before it enters the AXI NOC.
  • All transactions originating from the APU or RPU must be defined by a Memory Attribute nGnRnE or nGnRE to ensure AxCACHE[1] = 1’b0.
  • All transactions originating from PPU has no additional requirement necessary.