DMA_CONTROL (0x0A0) - 3.4 English

Versal Adaptive SoC CPM DMA and Bridge Mode for PCI Express Product Guide (PG347)

Document ID
Release Date
3.4 English
Table 1. DMA Control (0x0A0)
Bit Default Access Type Field Description
[31:1]   NA   Reserved
[0] 0 RW gen_qdma_reset When soft_reset is set, generates a soft reset to the DMA block. This bit is cleared after 100 cycles.

Writing a 1 to DMA_control[0] generates a soft reset on soft_reset_n (active-Low). A reset is asserted for 100 cycles, and following which of the signals will be deasserted.