DMA_CONTROL (0x0A0) - 3.4 English - PG347

Versal Adaptive SoC CPM DMA and Bridge Mode for PCI Express Product Guide (PG347)

Document ID
PG347
Release Date
2024-11-22
Version
3.4 English
Table 1. DMA Control (0x0A0)
Bit Default Access Type Field Description
[31:1]   NA   Reserved
[0] 0 RW gen_qdma_reset When this bit is set, example design generates a signal which resets QDMA interface logic. This bit is cleared after 100 cycles.

Writing a 1 to DMA_control[0] generates a soft reset on dma<0/1>_intrfc_resetn (active-Low). A reset is asserted for 100 cycles, and following which of the signals will be deasserted.