Bit | Default | Access Type | Field | Description |
---|---|---|---|---|
[31:1] | NA | Reserved | ||
[0] | 0 | RW | gen_qdma_reset | When this bit is set, example design generates a signal which resets QDMA interface logic. This bit is cleared after 100 cycles. |
Writing a 1 to DMA_control[0] generates a soft reset on dma<0/1>_intrfc_resetn (active-Low). A reset is asserted for 100 cycles, and following which of the signals will be deasserted.