Interrupt Request (IRQ) Routing and Programming for CPM5 - 3.4 English

Versal Adaptive SoC CPM DMA and Bridge Mode for PCI Express Product Guide (PG347)

Document ID
PG347
Release Date
2023-11-20
Version
3.4 English

This appendix includes guidance on Interrupt Request (IRQ) pins routing and programming for CPM5. Versal Adaptive SoC CPM DMA and Bridge Mode for PCI Express provides three independent IRQ pins routed to the Programmable Logic (PL) region as well as three independent IRQ pins routed to the hardened Processing System (PS) region. These IRQ pins are shared between the two PCIe controllers and all CPM5 use modes and can be programmed by user to route one or many Interrupt sources.

The three IRQ pins routed to the PL region are named cpm_misc_irq, cpm_cor_irq, and cpm_uncor_irq and are visible in the Vivado Block Diagram (BD) canvas at the Versal CIPS IP boundary. Although, the IRQ pins are named as miscellaneous, correctable, and uncorrectable respectively, they function identically from each other and have the same list of interrupt source to select from. Therefore, you can assume these IRQ pins as three separate general purpose IRQ pins.

The three IRQ pins routed to the PS regions are named similarly however they are not visible in the Vivado BD canvas and they are using hardened silicon routing. These paths are always enabled and no extra customization is required during CIPS IP customization to use it. These IRQ pins also function identically and have the same list of interrupt source to select from as the PL IRQ pins counterparts and can be used with the PL IRQ pins.

There are many Interrupt source to select from and the complete list is available in the Versal Adaptive SoC Register Reference (AM012). This appendix provides a use case example to showcase how the IRQ pins mux registers are programmed and includes firmware guidance to service the interrupt request.

Example: Generate Interrupt Request for Hot Reset

In this example, you will generate an interrupt whenever hot reset is received for PCIe0 controller and PCIe1 controller. You will route the interrupt generated from PCIe0 controller to the PS region while interrupt is generated from PCIe1 controller to the PL region. You will use the cpm_misc_irq pin as an example, but any other pins can also be used. Note that in this particular example, you will use the pcie_local_event interrupt line at the CPM5_SLCR mux level which is driven by CPM5_DMA_CSR.INT_DEC register. A high level block diagram of the interrupt routing is shown in the following diagram:

Figure 1. Interrupt Routing Diagram

Register programming to enable Hot Reset event interrupt
The following register shall be programmed by you at runtime to enable the interrupt:
  • For PCIe0 controller
    1. CPM5_SLCR.PS_MISC_IR_ENABLE set to 0x2 to select pcie0_err
    2. Read to confirm that CPM5_SLCR.PS_MISC_IR_MASK is cleared for bit[1] pcie0_err
    3. CPM5_SLCR.PCIE0_IR_ENABLE set to 0x1 to select pcie_local_event
    4. Read to confirm that CPM5_SLCR.PCIE0_IR_MASK is cleared for bit[0] pcie_local_event
    5. CPM5_DMA0_CSR.INT_MASK set to 0x8 to select hot_reset
    6. Read to confirm that CPM5_DMA0_CSR.INT_MASK is set for bit[3] hot_reset
  • For PCIe1 controller
    1. CPM5_SLCR.PL_MISC_IR_ENABLE set to 0x4 to select pcie1_err
    2. Read to confirm that CPM5_SLCR.PL_MISC_IR_MASK is cleared for bit[2] pcie1_err
    3. CPM5_SLCR.PCIE1_IR_ENABLE set to 0x1 to select pcie_local_event
    4. Read to confirm that CPM5_SLCR.PCIE1_IR_MASK is cleared for bit[0] pcie_local_event
    5. CPM5_DMA1_CSR.INT_MASK set to 0x8 to select hot_reset
    6. Read to confirm that CPM5_DMA1_CSR.INT_MASK is set for bit[3] hot_reset
Interrupt service routine
The following steps outline the recommended procedure to service the interrupt request:
  • For PCIe0 controller
    1. Upon receiving interrupt, read CPM5_SLCR.PS_MISC_IR_STATUS to confirm bit[1] pcie0_err is asserted
    2. CPM5_SLCR.PS_MISC_IR_DISABLE set to 0x2 to temporarily mask pcie0_err so further interrupt is not received while existing interrupt is being serviced
    3. Read CPM5_SLCR.PCIE0_IR_STATUS to confirm bit[0] pcie_local_event is asserted
    4. CPM5_SLCR.PCIE0_IR_DISABLE set to 0x1 to temporarily mask pcie_local_event
    5. Read CPM5_DMA0_CSR.INT_DEC to confirm bit [3] hot_reset is asserted.
    6. CPM5_DMA0_CSR.INT_MASK set to 0x0 to temporarily mask hot_reset
    7. Execute user-defined task for servicing Hot Reset event
    8. CPM5_DMA0_CSR.INT_DEC set to 0x8 to clear hot_reset
    9. CPM5_SLCR.PCIE0_IR_STATUS set to 0x1 to clear pcie_local_event
    10. CPM5_SLCR.PS_MISC_IR_STATUS set to 0x2 to clear pcie0_err
    11. Re-enable / unmask Hot Reset event interrupt source by programming the CPM5_SLCR.PS_MISC_IR_ENABLE, CPM5_SLCR.PCIE0_IR_ENABLE, and CPM5_DMA0_CSR.INT_MASK registers
  • For PCIe1 controller
    1. Upon receiving interrupt, read CPM5_SLCR.PL_MISC_IR_STATUS to confirm bit[2] pcie1_err is asserted
    2. CPM5_SLCR.PL_MISC_IR_DISABLE set to 0x4 to temporarily mask pcie1_err so further interrupt is not received while existing interrupt is being serviced
    3. Read CPM5_SLCR.PCIE1_IR_STATUS to confirm bit[0] pcie_local_event is asserted
    4. CPM5_SLCR.PCIE1_IR_DISABLE set to 0x1 to temporarily mask pcie_local_event
    5. Read CPM5_DMA1_CSR.INT_DEC to confirm bit [3] hot_reset is asserted.
    6. CPM5_DMA1_CSR.INT_MASK set to 0x0 to temporarily mask hot_reset
    7. Execute user-defined task for servicing Hot Reset event
    8. CPM5_DMA1_CSR.INT_DEC set to 0x8 to clear hot_reset
    9. CPM5_SLCR.PCIE1_IR_STATUS set to 0x1 to clear pcie_local_event
    10. CPM5_SLCR.PL_MISC_IR_STATUS set to 0x4 to clear pcie1_err
    11. Re-enable / unmask Hot Reset event interrupt source by programming the CPM5_SLCR.PL_MISC_IR_ENABLE, CPM5_SLCR.PCIE1_IR_ENABLE, and CPM5_DMA1_CSR.INT_MASK registers

Example: Generate Interrupt Request for MSI Interrupt as Root Port

In this example, you will generate an interrupt whenever MSI vector 0 interrupt is received for PCIe0 controller and PCIe1 controller. You will route the interrupt generated from PCIe0 controller to the PS region while the interrupt generated from PCIe1 controller to the PL region. You will use the cpm_misc_irq pin as an example, but any other pins can also be used. Note that in this particular example, you will use the pcie_msi0 interrupt line at the CPM5_SLCR mux level which is driven by CPM5_DMA_CSR.MSI_DEC_31_0 register. A high level block diagram of the interrupt routing is shown in the following diagram:

Figure 2. Interrupt Routing Diagram

Register programming to enable MSI vector 0 event interrupt
The following register shall be programmed by you at runtime to enable the interrupt:
  • For PCIe0 controller
    1. CPM5_SLCR.PS_MISC_IR_ENABLE set to 0x2 to select pcie0_err
    2. Read to confirm that CPM5_SLCR.PS_MISC_IR_MASK is cleared for bit[1] pcie0_err
    3. CPM5_SLCR.PCIE0_IR_ENABLE set to 0x2 to select pcie_msi0
    4. Read to confirm that CPM5_SLCR.PCIE0_IR_MASK is cleared for bit[1] pcie_msi0
    5. CPM5_DMA0_CSR.MSI_MASK_31_0 set to 0x1 to select MSI vector 0
    6. Read to confirm that CPM5_DMA0_CSR.MSI_MASK_31_0 is set for bit[0] MSI vector 0
  • For PCIe1 controller
    1. CPM5_SLCR.PL_MISC_IR_ENABLE set to 0x4 to select pcie1_err
    2. Read to confirm that CPM5_SLCR.PL_MISC_IR_MASK is cleared for bit[2] pcie1_err
    3. CPM5_SLCR.PCIE1_IR_ENABLE set to 0x2 to select pcie_msi0
    4. Read to confirm that CPM5_SLCR.PCIE1_IR_MASK is cleared for bit[1] pcie_msi0
    5. CPM5_DMA1_CSR.MSI_MASK_31_0 set to 0x1 to select MSI vector 0
    6. Read to confirm that CPM5_DMA1_CSR.MSI_MASK_31_0 is set for bit[0] MSI vector 0
Interrupt service routine
The following steps outlines the recommended procedure to service the interrupt request.
  • For PCIe0 controller
    1. Upon receiving interrupt, read CPM5_SLCR.PS_MISC_IR_STATUS to confirm bit[1] pcie0_err is asserted
    2. CPM5_SLCR.PS_MISC_IR_DISABLE set to 0x2 to temporarily mask pcie0_err so further interrupt is not received while existing interrupt is being serviced
    3. Read CPM5_SLCR.PCIE0_IR_STATUS to confirm bit[1] pcie_msi0 is asserted
    4. CPM5_SLCR.PCIE0_IR_DISABLE set to 0x2 to temporarily mask pcie_msi0
    5. Read CPM5_DMA0_CSR.MSI_DEC_31_0 to confirm bit [0] MSI vector 0 is asserted.
    6. CPM5_DMA0_CSR.MSI_MASK_31_0 set to 0x0 to temporarily mask MSI vector 0
    7. Execute user-defined task for servicing MSI interrupt
    8. CPM5_DMA0_CSR.MSI_DEC_31_0 set to 0x1 to clear MSI vector 0
    9. CPM5_SLCR.PCIE0_IR_STATUS set to 0x2 to clear pcie_msi0
    10. CPM5_SLCR.PS_MISC_IR_STATUS set to 0x2 to clear pcie0_err
    11. Re-enable / unmask FLR event interrupt source by programming the CPM5_SLCR.PS_MISC_IR_ENABLE, CPM5_SLCR.PCIE0_IR_ENABLE, and CPM5_DMA0_CSR.MSI_MASK_31_0 registers
  • For PCIe1 controller
    1. Upon receiving interrupt, read CPM5_SLCR.PL_MISC_IR_STATUS to confirm bit[2] pcie1_err is asserted
    2. CPM5_SLCR.PL_MISC_IR_DISABLE set to 0x4 to temporarily mask pcie1_err so further interrupt is not received while existing interrupt is being serviced
    3. Read CPM5_SLCR.PCIE1_IR_STATUS to confirm bit[1] pcie_msi0 is asserted
    4. CPM5_SLCR.PCIE1_IR_DISABLE set to 0x2 to temporarily mask pcie_msi0
    5. Read CPM5_DMA1_CSR.MSI_DEC_31_0 to confirm bit [0] MSI vector 0 is asserted.
    6. CPM5_DMA1_CSR.MSI_MASK_31_0 set to 0x0 to temporarily mask MSI vector 0
    7. Execute user-defined task for servicing MSI interrupt
    8. CPM5_DMA1_CSR.MSI_DEC_31_0 set to 0x1 to clear MSI vector 0
    9. CPM5_SLCR.PCIE1_IR_STATUS set to 0x2 to clear pcie_msi0
    10. CPM5_SLCR.PL_MISC_IR_STATUS set to 0x4 to clear pcie1_err
    11. Re-enable / unmask FLR event interrupt source by programming the CPM5_SLCR.PL_MISC_IR_ENABLE, CPM5_SLCR.PCIE1_IR_ENABLE, and CPM5_DMA1_CSR.MSI_MASK_31_0 registers