Customizable Example Design (CED) - 3.4 English - PG347

Versal Adaptive SoC CPM DMA and Bridge Mode for PCI Express Product Guide (PG347)
Document ID
PG347
Release Date
2024-11-22
Version
3.4 English

CPM5 QDMA

The following table describes the available CPM5 example design. All the listed example designs are based on VPK120 evaluation board or equivalent part.

Table 1. QDMA Example design
Top CED Name Preset Simulation/Implementation Description
Vsersal_CPM_QDMA_EP_Design CPM5_QDMA_Gen4x8_MM_ST_Design Implementation Functional example design.
CPM5_QDMA_Gen5x8_MM_Performance_Design Implementation AXI4 performance design.
CPM5_QDMA_Gen4x8_ST_Performance_Design Implementation AXI-ST performance design.
CPM5_QDMA_Dual_Gen4x8_MM_ST_Design Implementation Functional example design.
Versal_CPM_QDMA_EP_Simulation_Design No preset Simulation QDMA full functional simulation design.
Versal_CPM_Bridge RP_Design CPM5_PCIe_Controller0_Gen4x8_RootPort_Design Implementation RP design
CPM5_PCIe_Controller1_Gen4x8_RootPort_Design Implementation RP design
Versal_CPM_QDMA_EP_Design (Part Based) CPM5_QDMA_Gen5x8_ST_Performance_Design Implementation AXI-ST performance design.
CPM5_QDMA_Dual_Gen5x8_ST_Performance_Design Implementation AXI-ST performance design.

The associated drivers can be downloaded from GitHub.