USER_INTERRUPT_VECTOR (0x09C) - 3.4 English

Versal Adaptive SoC CPM DMA and Bridge Mode for PCI Express Product Guide (PG347)

Document ID
PG347
Release Date
2023-11-20
Version
3.4 English
Table 1. User Interrupt Vector (0x09C)
Bit Default Access Type Description
[31:0] 0 RW User Interrupt Vector

The user_interrupt_mask[31:0] and user_interrupt_vector[31:0] registers are provided as an example design for user interrupt aggregation that can generate a user interrupt for a function. The user_interrupt_mask[31:0] is anded (bitwire and) with user_interrupt_vector[31:0] and a user interrupt is generated. The user_interrupt_vector[31:0] is clear on read register.

To generate a user interrupt:

  1. Write the function number at user_interrupt[19:12]. This corresponds to which function generates the usr_irq_in_fnc user interrupt.
  2. Write the MSI-X Vector number at user_interrupt[8:4]. This corresponds to which entry in MSI-X table is set up for the usr_irq_in_vec user interrupt.
  3. Write mask value in the user_interrupt_mask[31:0] register.
  4. Write the interrupt vector value in the user_interrupt_vector[31:0] register.

This generates a user interrupt to the DMA block.

There are two way to generate user interrupt:

  • Write to user_interrupt[0], or
  • Write to the user_interrupt_vector[31:0] register with mask set.