CPM5_QDMA_Dual_Gen5x8_ST_Performance_Design - 3.4 English

Versal Adaptive SoC CPM DMA and Bridge Mode for PCI Express Product Guide (PG347)

Document ID
PG347
Release Date
2023-11-20
Version
3.4 English

CPM5 Dual Controller QDMA0 and QDMA1 with Gen5x8 AXI4 and AXI4-Stream performance example design

  • The design targets "vsva2785-3HP-e-S" part and it supports synthesis and implementation flows
  • This design has both CPM5–QDMA0 and CPM5-QDMA1 enabled in Gen5x8, AXI4-Stream configuration as an End Point
  • Capable of demonstrating AXI-ST performance
  • Capable of performing in Internal modes or cache bypass mode or in Simple bypass mode
  • To change the data packet size on C2H direction you need to set example design register offset 0x90 to desired value