Descriptor Bypass Interface

Descriptor Bypass Interface - 3.4 English

Versal Adaptive SoC CPM DMA and Bridge Mode for PCI Express Product Guide (PG347)

Document ID

PG347

Release Date

2024-05-30

Version

3.4 English

These ports are present if either Descriptor Bypass for Read (H2C) or Descriptor Bypass for Write (C2H) are selected in the PCIe DMA Tab in the Vivado IDE. Each binary bit corresponds to a channel, and LSB corresponds to Channel 0. Value 1 in bit positions means the corresponding channel descriptor bypass is enabled.

Table 1. H2C 0-3 Descriptor Bypass Interface description
Port	Direction	Description
dma0_h2c_dsc_byp_x_ready	O	Channel is ready to accept new descriptors. After dma0_h2c_dsc_byp_ready is deasserted, one additional descriptor can be written. The Control register 'Run' bit must be asserted before the channel accepts descriptors.
dma0_h2c_dsc_byp_x_load	I	Write the descriptor presented at dma0_h2c_dsc_byp_data into the channel’s descriptor buffer.
dma0_h2c_dsc_byp_src_x_addr[63:0]	I	Descriptor source address to be loaded.
dma0_h2c_dsc_byp_dst_x_addr[63:0]	I	Descriptor destination address to be loaded.
dma0_h2c_dsc_byp_x_len[27:0]	I	Descriptor length to be loaded.
dma0_h2c_dsc_byp_x_ctl[15:0]	I	Descriptor control to be loaded. [0]: Stop. Set to 1 to stop fetching next descriptor. [1]: Completed. Set to 1 to interrupt after the engine has completed this descriptor. [3:2]: Reserved. [4]: EOP. End of Packet for AXI-Stream interface. [15:5]: Reserved. All reserved bits can be forced to 0s.
_x in the signal name changes based on the channel number 0, 1, 2, and 3. For example, for channel 0 use the `dma0_h2c_dsc_byp_0_ctl[15:0]` port, and for channel 1 use the`dma0_h2c_dsc_byp_1_ctl[15:0]` port.

Table 2. C2H 0-3 Descriptor Bypass Ports
Port	Direction	Description
dma0_c2h_dsc_byp_x_ready	O	Channel is ready to accept new descriptors. After dma0_c2h_dsc_byp_ready is deasserted, one additional descriptor can be written. The Control register 'Run' bit must be asserted before the channel accepts descriptors.
dma0_c2h_dsc_byp_x_load	I	Descriptor presented at dma0_c2h_dsc_byp_* is valid.
dma0_c2h_dsc_byp_src_x_addr[63:0]	I	Descriptor source address to be loaded.
dma0_c2h_dsc_byp_dst_x_addr[63:0]	I	Descriptor destination address to be loaded.
dma0_c2h_dsc_byp_x_len[27:0]	I	Descriptor length to be loaded.
dma0_c2h_dsc_byp_x_ctl[15:0]	I	Descriptor control to be loaded. [0]: Stop. Set to 1 to stop fetching next descriptor. [1]: Completed. Set to 1 to interrupt after the engine has completed this descriptor. [3:2]: Reserved. [4]: EOP. End of Packet for AXI-Stream interface. [15:5]: Reserved. All reserved bits can be forced to 0s.
_x in the signal name changes based on the channel number 0, 1, 2, and 3. For example, for channel 0 use the `dma0_c2h_dsc_byp_0_ctl[15:0]` port, and for channel 1 use the`dma0_c2h_dsc_byp_1_ctl[15:0]` port.

The following timing diagram shows how to input the descriptor in descriptor bypass mode. When dma0_<h2c|c2h>_dsc_byp_ready is asserted, a new descriptor can be pushed in with the dma0_<h2c|c2h>_dsc_byp_load signal.

Figure 1. Timing Diagram for Descriptor Bypass Mode

Important: Immediately after dma0_<h2c|c2h>_dsc_byp_ready is deasserted, one more descriptor can be pushed in. In the above timing diagram, a descriptor is pushed in when dma0_<h2c|c2h>_dsc_byp_ready is deasserted.