DMA C2H Stream - 3.4 English

Versal Adaptive SoC CPM DMA and Bridge Mode for PCI Express Product Guide (PG347)

Document ID
Release Date
3.4 English

For card-to-host transfers, the data is received from the AXI4-Stream interface and written to the destination address. Packets can span multiple descriptors. The C2H channel accepts data when it is enabled, and has valid descriptors. As data is received, it fills descriptors in order. When a descriptor is filled completely or closed due to an end of packet on the interface, the C2H channel writes back information to the writeback address on the host with pre-defined WB Magic value 16'h52b4 (Table 2), and updated EOP and Length as appropriate. For valid data cycles on the C2H AXI4-Stream interface, all data associated with a given packet must be contiguous.

Note: C2H Channel Writeback information is different then Poll mode updates. C2H Channel Writeback information provides the driver current length status of a particular descriptor. This is different from Pollmode_*, as is described in Poll Mode.

The tkeep bits must be all 1s except for the last data transfer of a packet. On the last transfer of a packet, when tlast is asserted, you can specify a tkeep that is not all 1s to specify a data cycle that is not the full datapath width. The asserted tkeep bits need to be packed to the lsb, indicating contiguous data. If tlast is asserted and tkeep has all zero's, this is not a valid combination for DMA to function properly.

The length of a C2H Stream descriptor (the size of the destination buffer) must always be a multiple of 64 bytes.

Table 1. C2H Stream Writeback Format
Offset Fields
0x0 WB Magic[15:0] Reserved [14:0] Status[0]
0x04 Length[31:0]
Table 2. C2H Stream Writeback Fields
Field Bit Index Sub Field Description
Status 0 EOP End of packet
Reserved 14:0   Reserved
WB Magic 15:0   16’h52b4. Code to verify the C2H writeback is valid.
Length 31:0   Length of the data in bytes.
Note: C2H Streaming writeback address cannot cross 4K boundary.