CPM5 QDMA1 Gen5x8 AXI4 performance example design:
- This design has CPM5 – QDMA1 enabled in Gen5x8 configuration as an End Point
- The design targets VPK120 board and it supports synthesis and implementation flows
- The design has AXI4 datapath accessing DDR over NoC
- Capable of demonstrating the QDMA MM performance
To achieve maximum performance for AXI4 transfers, you need to use both the NoC channels 0 and 1. Both NoC channels can be used by programming the Host Profile settings. For more information, see Host Profile.
For example all even queues can be assigned to Host ID 0 and odd queues can be assigned to Host ID 1. During Q context programming, all even queues can be assigned with host ID 0 and all odd queues can be assigned to host ID 1. In this manner there is equal traffic on NoC 0 and NoC1 channels. This maximizes the MM throughput from CPM to NoC to DDR memory.