QDMA_PF_MAILBOX (0x2400) - 3.4 English

Versal Adaptive SoC CPM DMA and Bridge Mode for PCI Express Product Guide (PG347)

Document ID: PG347
Release Date: 2024-05-30
Version: 3.4 English

Table 1. QDMA_PF_MAILBOX (0x2400) Register Space
Register	Address	Description
Function Status Register (0x2400)	0x2400	Status bits
Function Command Register (0x2404)	0x2404	Command register bits
Function Interrupt Vector Register (0x2408)	0x2408	Interrupt vector register
Target Function Register (0x240C)	0x240C	Target Function register
Function Interrupt Vector Register (0x2410)	0x2410	Interrupt Control Register
RTL Version Register (0x2414)	0x2414	RTLVersion Register
PF Acknowledgment Registers (0x2420-0x243C)	0x2420-0x243C	PF acknowledge
FLR Control/Status Register (0x2500)	0x2500	FLR control and status
Incoming Message Memory (0x2C00-0x2C7C)	0x2C00-0x2C7C	Incoming message (128 bytes)
Outgoing Message Memory (0x3000-0x307C)	0x3000-0x307C	Outgoing message (128 bytes)

Mailbox Addressing

PF addressing: Addr = PF_Bar_offset + CSR_addr
VF addressing: Addr = VF_Bar_offset + VF_Start_offset + VF_offset + CSR_addr