Clocking - 3.4 English

Versal Adaptive SoC CPM DMA and Bridge Mode for PCI Express Product Guide (PG347)

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DMA Clock

QDMA and AXI Bridge run on the clock that is provided by the user. This is a change from CPM4 (where the IP provides the clock). You must provide a clock dma<n>_intrfc_clk, that is used by the IP. All the input and output ports are driven or loaded using this clock. Because this is an independent clock provided by the user, there are some restrictions on clock frequency based on the IP configurations that are listed below:

Table 1. Clock Frequency
Configuration Options Frequency
Gen3x16 250 MHz
Gen4x8 250 MHz
Gen4x16 433 MHz 1
Gen5x8 433 MHz 1
  1. For 433 MHz frequency, you need to have a -3HP device.

The input clock frequency (dma<n>_interfc_clk and cpm_pl_axi<n>_clk for Gen3x16 and Gen4x8 configurations is 250 MHz. For Gen4x16 and Gen5x8 configurations, the maximum input clock frequency allowed is 433 MHz for a -3HP device. For other device speed grades, refer to the corresponding device datasheet to know the maximum frequency applicable to those devices.

For the QDMA1 AXI-MM interface, there are two more clock inputs that you must provide, cpm_pl_axi0_clk and cpm_pl_axi1_clk.

PCIe Ref Clock

Each link partner device shares the same reference clock source. The following figures show a system using a 100 MHz reference clock. Even if the device is part of an embedded system, if the system uses commercial PCI ExpressĀ® root complexes or switches along with typical motherboard clocking schemes, synchronous clocking should be used.

Note: The following figures are high-level representations of the board layout. Ensure that coupling, termination, and details are correct when laying out a board.
Figure 1. Embedded System Using 100 MHz Reference Clock
Figure 2. Open System Add-In Card Using 100 MHz Reference Clock