Signal Name 1 | Direction | Description |
---|---|---|
dma0_m_axis_h2c_x_tready | I | Assertion of this signal by the user logic indicates that it is ready to accept data. Data is transferred across the interface when dma0_m_axis_h2c_tready and dma0_m_axis_h2c_tvalid are asserted in the same cycle. If the user logic deasserts the signal when the valid signal is High, the DMA keeps the valid signal asserted until the ready signal is asserted. |
dma0_m_axis_h2c_x_tlast | O | The DMA asserts this signal in the last beat of the DMA packet to indicate the end of the packet. |
dma0_m_axis_h2c_x_tdata [DATA_WIDTH-1:0] |
O | Transmit data from the DMA to the user logic. |
dma0_m_axis_h2c_x_tkeep [DATA_WIDTH/8-1:0] |
O | tkeep will be all 1s except when dma0_m_axis_h2c_x_tlast is
asserted. |
dma0_m_axis_h2c_x_tvalid | O | The DMA asserts this whenever it is driving valid data on dma0_m_axis_h2c_tdata. |
dma0_m_axis_h2c__x_tuser [DATA_WIDTH/8-1:0] |
O | Parity bits. This port is enabled only in Propagate Parity mode. |
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