AXI Slave Interface - 3.4 English

Versal Adaptive SoC CPM DMA and Bridge Mode for PCI Express Product Guide (PG347)

Document ID
PG347
Release Date
2024-05-30
Version
3.4 English

AXI Bridge Slave ports are connected from the AMD Versal device Network on Chip (NoC) to the CPM DMA internally. For Slave Bridge AXI4 details, see Versal Adaptive SoC Programmable Network on Chip and Integrated Memory Controller LogiCORE IP Product Guide (PG313).

To access XDMA registers, you must follow the protocols outlined in the AXI Slave Bridge Register Limitations section.